公开(公告)号：WO2012006553A3

公开(公告)日：2012-04-19

申请号：PCT/US2011043402

申请日：2011-07-08

Applicant: ALTERA CORP ,  KIPPER MICHAEL HOWARD ,  FENDER JOSHUA DAVID ,  AZIZI NAVID ,  GOLDMAN DAVID SAMUEL

Inventor： KIPPER MICHAEL HOWARD ,  FENDER JOSHUA DAVID ,  AZIZI NAVID ,  GOLDMAN DAVID SAMUEL

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/82

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.

Abstract translation: 介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。 在一种方法中，CAD工具接收到IC参数的值分配。 值分配作为值分配的范围输入，或作为可能的值分配列表。 此外，该方法包括用于确定I / O块中的每个输入/输出（I / O）引脚的最小和最大路径延迟的操作，使得满足接收的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。 切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。 此外，还包括其他方法操作，用于路由到I / O引脚的路径，以满足实际切换时间，并为IC创建满足实际切换时间的设计。

公开(公告)号：WO2012006553A2

公开(公告)日：2012-01-12

申请号：PCT/US2011/043402

申请日：2011-07-08

Applicant: ALTERA CORPORATION ,  KIPPER, Michael, Howard ,  FENDER, Joshua, David ,  AZIZI, Navid ,  GOLDMAN, David, Samuel

Inventor： KIPPER, Michael, Howard ,  FENDER, Joshua, David ,  AZIZI, Navid ,  GOLDMAN, David, Samuel

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/82

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.

Abstract translation: 介绍了用计算机辅助设计（CAD）工具设计的用于降低集成电路（IC）中同时开关噪声（SSN）的方法和装置。 在一种方法中，CAD工具接收IC参数的值分配。 价值分配是作为一系列价值分配或作为可能的价值分配列表输入的。 此外，该方法包括用于确定I / O块中的每个输入/输出（I / O）引脚的最小和最大路径延迟的操作，以使得接收到的值分配得到满足。 I / O引脚的实际切换时间会及时分散以减少I / O引脚中的SSN。 开关时间分散开来，使得开关时间落在相应I / O引脚的最小和最大路径延迟之间。 此外，还包括其他方法操作，用于路由到I / O引脚的路径以满足实际切换时间，并为IC创建满足实际切换时间的设计。