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    APPARATUS AND SYSTEM FOR DIGITALLY CONTROLLED OSCILLATOR
    2.
    发明申请
    APPARATUS AND SYSTEM FOR DIGITALLY CONTROLLED OSCILLATOR 审中-公开
    数字控制振荡器的装置和系统

    公开(公告)号：WO2013141863A1

    公开(公告)日：2013-09-26

    申请号：PCT/US2012/030151

    申请日：2012-03-22

    Applicant: LOTFY, Amr M. ,  ABDELSALAM, Mohamed A. ,  EL MAHALAWY, Mohammed W. ,  KURD, Nasser A. ,  ABDELMONEUM, Mohamed A.

    Inventor： LOTFY, Amr M. ,  ABDELSALAM, Mohamed A. ,  EL MAHALAWY, Mohammed W. ,  KURD, Nasser A. ,  ABDELMONEUM, Mohamed A.

    IPC: H03L7/099 ,  H03K3/03

    CPC classification number: H03L7/00 ,  H03K3/0315 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0992

    Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

    Abstract translation: 这里描述了用于数字控制振荡器（DCO）的装置和系统。 该装置包括电压调节器以提供可调电源; 以及DCO，用于产生输出时钟信号，所述DCO包括一个或多个延迟元件，每个延迟元件可操作以经由所述可调节电源改变其传播延迟，其中每个延迟元件包括具有可调驱动强度的逆变器，其中所述逆变器 由可调电源供电。 该装置还包括数字控制器，用于产生用于指示电压调节器调节可调电源的电压电平的第一信号。

    LOW POWER, JITTER AND LATENCY CLOCKING WITH COMMON REFERENCE CLOCK SIGNALS FOR ON-PACKAGE INPUT/OUTPUT INTERFACES
    3.
    发明申请
    LOW POWER, JITTER AND LATENCY CLOCKING WITH COMMON REFERENCE CLOCK SIGNALS FOR ON-PACKAGE INPUT/OUTPUT INTERFACES 审中-公开
    低功耗，抖动和延迟时钟与通用输入/输出接口的通用参考时钟信号

    公开(公告)号：WO2013095549A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/066990

    申请日：2011-12-22

    Applicant: INTEL CORPORATION ,  KURD, Nasser A. ,  THOMAS, Thomas P.

    Inventor： KURD, Nasser A. ,  THOMAS, Thomas P.

    IPC: G06F1/00 ,  G06F1/04 ,  G06F13/14 ,  H03L7/08

    CPC classification number: H03L7/22 ,  G06F1/06 ,  G06F1/32

    Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.

    Abstract translation: 低功耗，抖动和延迟时钟，具有用于封装输入/输出接口的公共参考时钟信号。 第一管芯上的主器件中的滤波器锁相环电路提供具有2F频率的时钟信号。 第一管芯上的主器件中的本地锁相环电路与滤波器锁相环耦合，以通过本地时钟分频器电路为主器件的功能部件提供时钟信号，以向功能部件提供F的时钟信号 组件。 第二管芯上的从器件中的远程锁相环电路与滤波器锁相环耦合，以通过本地时钟分频器电路向从器件的一个或多个功能部件提供时钟信号，以提供F 到功能组件。

    SENSE AMPLIFIER
    5.
    发明申请
    SENSE AMPLIFIER 审中-公开
    感应放大器

    公开(公告)号：WO2000026907A1

    公开(公告)日：2000-05-11

    申请号：PCT/US1999025628

    申请日：1999-11-01

    Applicant: INTEL CORPORATION ,  KURD, Nasser, A.

    Inventor： INTEL CORPORATION

    IPC: G11B19/00

    CPC classification number: H03F3/45237 ,  H03F2203/45454 ,  H03K19/018528

    Abstract: A sense amplifier (500) comprising first (518, 520) and second (522, 524) CMOS inverters, an pMOS current mirror (502, 504), an nMOS current mirror (506, 508), a source pMOSFET (510) to source current, and a sink nMOSFET (512) to sink current. The gate voltage of the first CMOS inverter (518, 520) is the input voltage and the gate voltage of the second CMOS inverter (522, 524) is at the reference voltage. The output voltage (516) is at the drains of the first CMOS inverter. The pMOS and nMOS current mirrors provide active loads to the first and second CMOS inverters. The sense amplifier is self-biasing by connecting the gate of the source pMOSFET to the gates of the pMOS current mirror and by connecting the gate of the sink nMOSFET to the gates of the nMOS current mirror.

    Abstract translation: 包括第一（518,520）和第二（522,524）CMOS反相器的读出放大器（500），pMOS电流镜（502,504），nMOS电流镜（506,508），源pMOSFET（510） 源电流和用于吸收电流的sink nMOSFET（512）。 第一CMOS反相器（518,520）的栅极电压是第二CMOS反相器（522,524）的输入电压，栅极电压处于参考电压。 输出电压（516）位于第一CMOS反相器的漏极处。 pMOS和nMOS电流镜向第一和第二CMOS反相器提供有源负载。 读出放大器通过将源极pMOSFET的栅极连接到pMOS电流镜的栅极并通过将sink nMOSFET的栅极连接到nMOS电流镜的栅极来进行自偏置。

    SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE
    6.
    发明申请
    SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE 审中-公开
    用于定位相位锁定环路功率的系统和方法

    公开(公告)号：WO2013095390A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/066205

    申请日：2011-12-20

    Applicant: INTEL CORPORATION ,  KURD, Nasser A. ,  GROSSNICKLE, Vaughn J.

    Inventor： KURD, Nasser A. ,  GROSSNICKLE, Vaughn J.

    IPC: H03L7/08 ,  G06F1/32

    CPC classification number: H03L7/08 ,  G06F1/08 ,  G06F1/3296 ,  Y02D10/172

    Abstract: Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

    Abstract translation: 描述了用于提供具有可缩放功率的PLL架构的装置，系统和方法。 在一个实施例中，系统包括具有电压调节器的一个或多个处理单元，用于为耦合到电压调节器的锁相环（PLL）电路产生可控地调节的电源电压。 PLL电路将参考时钟信号的相位和频率与生成的反馈时钟信号的相位和频率进行比较，并且基于该比较生成输出信号。 跟踪单元基于系统的操作频率来调节可调节的电源电压。

    A METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES
    7.
    发明申请
    A METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES 审中-公开
    快速唤醒模拟偏差的方法和装置

    公开(公告)号：WO2012012211A3

    公开(公告)日：2012-04-05

    申请号：PCT/US2011043514

    申请日：2011-07-11

    Applicant: INTEL CORP ,  MOSALIKANTI PRAVEEN ,  SRIDHARAN HARISHANKAR ,  SCHNEIDER JACOB ,  GORUR PUSHKAR ,  KURD NASSER A

    Inventor： MOSALIKANTI PRAVEEN ,  SRIDHARAN HARISHANKAR ,  SCHNEIDER JACOB ,  GORUR PUSHKAR ,  KURD NASSER A

    IPC: H03K17/04 ,  H03K5/13

    CPC classification number: H03K17/22 ,  H03K19/0008

    Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

    Abstract translation: 这里描述的是以最小延迟唤醒模拟偏置信号的方法和设备。 该设备包括：第一逻辑单元，用于响应于断电事件而经由第一预定信号调整门控偏置信号的信号电平; 比较器，其可操作以比较所述门控偏置信号与非门控偏置信号，且可操作以产生指示所述比较结果的输出信号; 以及自定时逻辑单元，其耦合到所述比较器并且可操作以响应于所述断电事件和所述输出信号的结束而产生唤醒信号。

    A METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES
    8.
    发明申请
    A METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES 审中-公开
    用于快速唤醒模拟偏差的方法和装置

    公开(公告)号：WO2012012211A2

    公开(公告)日：2012-01-26

    申请号：PCT/US2011/043514

    申请日：2011-07-11

    Applicant: INTEL CORPORATION ,  MOSALIKANTI, Praveen ,  SRIDHARAN, Harishankar ,  SCHNEIDER, Jacob ,  GORUR, Pushkar ,  KURD, Nasser A.

    Inventor： MOSALIKANTI, Praveen ,  SRIDHARAN, Harishankar ,  SCHNEIDER, Jacob ,  GORUR, Pushkar ,  KURD, Nasser A.

    IPC: H03K17/04 ,  H03K5/13

    CPC classification number: H03K17/22 ,  H03K19/0008

    Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

    Abstract translation: 这里描述了以最小延迟来唤醒模拟偏置信号的方法和装置。 该装置包括第一逻辑单元，用于响应于断电事件经由第一预定信号调节门控偏置信号的信号电平; 比较器，用于将门控偏置信号与非门控偏置信号进行比较，并且可操作以产生指示比较结果的输出信号; 以及耦合到所述比较器的自定时逻辑单元，用于响应于所述断电事件和所述输出信号的结束而产生唤醒信号。

    DIGITAL CLOCK SKEW DETECTION AND PHASE ALIGNMENT
    9.
    发明申请
    DIGITAL CLOCK SKEW DETECTION AND PHASE ALIGNMENT 审中-公开
    数字时钟检测和相位对准

    公开(公告)号：WO0223715A3

    公开(公告)日：2003-02-06

    申请号：PCT/US0127652

    申请日：2001-09-07

    Applicant: INTEL CORP ,  BARKATULLAH JAVED ,  KURD NASSER

    Inventor： BARKATULLAH JAVED ,  KURD NASSER

    IPC: G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/15 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089 ,  G01R25/08

    CPC classification number: H03D13/003 ,  G06F1/10 ,  H03K5/133 ,  H03K5/15013 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/089

    Abstract: A skew measure circuit (108), an exclusion circuit, and an up/down counter (116) are connected to form a skew detection circuit. The skew measure circuit (108) asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit (112) provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure cicuit is experiencing metastability. The up/down counter's count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.

    Abstract translation: 连接倾斜测量电路（108），排除电路和升降计数器（116）以形成偏斜检测电路。 如果第一输入时钟引导第二输入时钟，则偏斜测量电路（108）确定第一输出信号，并且如果第二时钟引导第一时钟则断言第二输出信号。 排除电路（112）提供表示歪斜测量电路的输出的第一和第二数字脉冲信号。 排除电路也可以防止这些脉冲信号的状态发生变化，只要倾斜测量结果正在经历亚稳态。 升/减计数器的计数响应于第一脉冲信号而增加，并响应于另一个脉冲信号递减。

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