公开(公告)号：WO0223715A3

公开(公告)日：2003-02-06

申请号：PCT/US0127652

申请日：2001-09-07

Applicant: INTEL CORP ,  BARKATULLAH JAVED ,  KURD NASSER

Inventor： BARKATULLAH JAVED ,  KURD NASSER

IPC: G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/15 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089 ,  G01R25/08

CPC classification number: H03D13/003 ,  G06F1/10 ,  H03K5/133 ,  H03K5/15013 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/089

Abstract: A skew measure circuit (108), an exclusion circuit, and an up/down counter (116) are connected to form a skew detection circuit. The skew measure circuit (108) asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit (112) provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure cicuit is experiencing metastability. The up/down counter's count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.

Abstract translation: 连接倾斜测量电路（108），排除电路和升降计数器（116）以形成偏斜检测电路。 如果第一输入时钟引导第二输入时钟，则偏斜测量电路（108）确定第一输出信号，并且如果第二时钟引导第一时钟则断言第二输出信号。 排除电路（112）提供表示歪斜测量电路的输出的第一和第二数字脉冲信号。 排除电路也可以防止这些脉冲信号的状态发生变化，只要倾斜测量结果正在经历亚稳态。 升/减计数器的计数响应于第一脉冲信号而增加，并响应于另一个脉冲信号递减。

公开(公告)号：WO2004095240A3

公开(公告)日：2005-06-02

申请号：PCT/US2004003386

申请日：2004-02-06

Applicant: INTEL CORP

Inventor： KURD NASSER ,  BARKATULLAH JAVED

IPC: G01R31/28 ,  G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  H03B1/00 ,  H03K5/00 ,  H03L1/00 ,  H03L7/06

CPC classification number: G01R19/16519 ,  G01K7/32 ,  G01R19/16552 ,  G01R19/16566 ,  G01R31/275 ,  G06F1/08 ,  H03L7/06

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract translation: 片上电压和/或频率检测器。 一方面，自适应频率时钟生成电路包括下降检测器，用于检测电源电压电平并且使得相应地调整芯片上时钟信号的频率。

公开(公告)号：AU8882301A

公开(公告)日：2002-03-26

申请号：AU8882301

申请日：2001-09-07

Applicant: INTEL CORP

Inventor： BARKATULLAH JAVED ,  KURD NASSER

IPC: G06F1/10 ,  H03D13/00 ,  H03K5/13 ,  H03K5/15 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089

Abstract: A skew measure circuit, an exclusion circuit, and an up/down counter are connected to form a skew detection circuit. The skew measure circuit asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure circuit is experiencing metastability. The up/down counter's count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.