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    ABOVE MOTHERBOARD INTERPOSER WITH PERIPHERAL CIRCUITS
    2.
    发明专利
    ABOVE MOTHERBOARD INTERPOSER WITH PERIPHERAL CIRCUITS 未知

    公开(公告)号：SG195030A1

    公开(公告)日：2013-12-30

    申请号：SG2013085261

    申请日：2012-03-30

    Applicant: MORGAN WEISS TECHNOLOGIES INC

    Inventor： JOHNSON MORGAN ,  WEISS FREDERICK G

    Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

    Stacked and folded above motherboard interposer
    6.
    发明授权
    Stacked and folded above motherboard interposer 有权

    公开(公告)号：US10884955B2

    公开(公告)日：2021-01-05

    申请号：US16578804

    申请日：2019-09-23

    Applicant: MORGAN/WEISS TECHNOLOGIES INC.

    Inventor： Morgan Johnson ,  Frederick G. Weiss

    IPC: H05K7/00 ,  G06F13/16 ,  H05K1/02 ,  H05K1/18 ,  H01L23/32 ,  G06F1/32 ,  H05K1/11 ,  H05K1/14 ,  G06F13/40 ,  G11C5/04 ,  H01L23/498

    Abstract: A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between the peripheral circuit and the main processor, wherein the at least two interposer substrates are stacked such that the at least two peripheral circuits on each interposer substrate are stacked with the at least two peripheral circuits on another of the at least two interposer substrates.

    ABOVE MOTHERBOARD INTERPOSER WITH QUARTER WAVELENGTH ELECTRICAL PATHS
    8.
    发明申请
    ABOVE MOTHERBOARD INTERPOSER WITH QUARTER WAVELENGTH ELECTRICAL PATHS 有权
    上面带有四分之一波长电路的主板插座

    公开(公告)号：US20150313017A1

    公开(公告)日：2015-10-29

    申请号：US14790302

    申请日：2015-07-02

    Applicant: MORGAN / WEISS TECHNOLOGIES INC.

    Inventor： Morgan Johnson ,  Frederick G. Weiss

    IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02

    CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.

    Abstract translation: 多层插入器衬底包括多层单个插入器衬底。 每个单个插入器衬底具有第一内插器互连阵列，每个插入器互连在插入器互连的第一阵列中对应于处理器互连阵列中的互连，插入器互连的第二阵列，插入器互连的第二阵列中的每个插入器互连 对应于电路基板上的电路互连阵列，以及与插入器互连的第一阵列中的至少一个互连相关联的插入器基板中的至少一个导电迹线。 导电迹线具有平行于插入器基板的平行部分，使得互连和第二插入器互连阵列中的相应的一个插入器互连之间不存在电连接。 每个单个插入器上的外围电路的连接阵列连接到至少一个导电迹线。

    Above motherboard interposer with quarter wavelength electrical paths
    9.
    发明授权
    Above motherboard interposer with quarter wavelength electrical paths 有权
    在主板上插入四分之一波长的电路径

    公开(公告)号：US09357648B2

    公开(公告)日：2016-05-31

    申请号：US14790302

    申请日：2015-07-02

    Applicant: MORGAN / WEISS TECHNOLOGIES INC.

    Inventor： Morgan Johnson ,  Frederick G. Weiss

    IPC: H05K1/11 ,  G06F1/32 ,  H05K1/02 ,  H01L23/32 ,  H05K1/14 ,  H05K1/18

    CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.

    Abstract translation: 多层插入器衬底包括多层单个插入器衬底。 每个单个插入器衬底具有第一内插器互连阵列，每个插入器互连在插入器互连的第一阵列中对应于处理器互连阵列中的互连，插入器互连的第二阵列，插入器互连的第二阵列中的每个插入器互连 对应于电路基板上的电路互连阵列，以及与插入器互连的第一阵列中的至少一个互连相关联的插入器基板中的至少一个导电迹线。 导电迹线具有平行于插入器基板的平行部分，使得互连和第二插入器互连阵列中的相应的一个插入器互连之间不存在电连接。 每个单个插入器上的外围电路的连接阵列连接到至少一个导电迹线。

    STACKED AND FOLDED ABOVE MOTHERBOARD INTERPOSER
    10.
    发明申请
    STACKED AND FOLDED ABOVE MOTHERBOARD INTERPOSER 审中-公开

    公开(公告)号：US20200019519A1

    公开(公告)日：2020-01-16

    申请号：US16578804

    申请日：2019-09-23

    Applicant: MORGAN / WEISS TECHNOLOGIES INC.

    Inventor： Morgan Johnson ,  Frederick G. Weiss

    IPC: G06F13/16 ,  H05K1/18 ,  H05K1/02 ,  H01L23/498 ,  G11C5/04 ,  G06F13/40 ,  H05K1/14 ,  H05K1/11 ,  G06F1/32 ,  H01L23/32

    Abstract: A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between the peripheral circuit and the main processor, wherein the at least two interposer substrates are stacked such that the at least two peripheral circuits on each interposer substrate are stacked with the at least two peripheral circuits on another of the at least two interposer substrates.

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