公开(公告)号：WO2008082938A3

公开(公告)日：2008-12-11

申请号：PCT/US2007087766

申请日：2007-12-17

Applicant: IBM ,  FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

Inventor： FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

IPC: G06F17/50 ,  G06F7/62 ,  G06F19/00

CPC classification number: G06F17/5009 ,  G06F2217/16

Abstract: A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N interconnect layers into multiple pixels, and (iii) determining a first path of the traveling particle in a first interconnect layer of the N interconnect layers, (iv) identifying M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle, M being a positive integer, and (v) determining a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels.

Abstract translation: 确定设计结构相对于行进粒子的停止能力的方法。 该方法包括（i）提供设计结构的设计信息，该设计结构包括包含N个互连层的后端行层，N是正整数，（ii）将N个互连层中的每个互连层分成多个像素 （iii）确定N个互连层中的第一互连层中的行进粒子的第一路径，（iv）识别在行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，M （v）确定由于其完全穿过M个路径像素的第一像素而由行进粒子损失的第一损失能量。

公开(公告)号：WO2010042263A1

公开(公告)日：2010-04-15

申请号：PCT/US2009/051213

申请日：2009-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MURRAY, Conal E. ,  YANG, Chih-Chao

Inventor： MURRAY, Conal E. ,  YANG, Chih-Chao

IPC: C25D5/02

CPC classification number: H01L21/76877 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

Abstract: Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss.

Abstract translation: 提供了包括表面修复材料（例如贵金属或贵金属合金）的半导体互连结构，其填充位于导电材料内的空心金属相关缺陷。 用表面修复材料填充中空金属相关缺陷改善了结构的电迁移（EM）可靠性以及降低了在线缺陷相关产量损失。

公开(公告)号：WO2011119717A1

公开(公告)日：2011-09-29

申请号：PCT/US2011/029601

申请日：2011-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COHEN, Guy ,  MURRAY, Conal E. ,  ROOKS, Michael J.

Inventor： COHEN, Guy ,  MURRAY, Conal E. ,  ROOKS, Michael J.

IPC: H01L27/105

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract translation: 提供了在纳米级基于沟道的场效应晶体管（FET）中嵌入硅锗（e-SiGe）源极和漏极应力的技术。 一方面，制造FET的方法包括以下步骤。 提供其上具有电介质的掺杂衬底。 在电介质上放置至少一个硅（Si）纳米线。 掩模纳米线的一个或多个部分，使纳米线的其它部分暴露出来。 外延锗（Ge）生长在纳米线的暴露部分上。 外延Ge与纳米线中的Si相互扩散，以形成纳米线中嵌入纳米线中的压应变的SiGe区域。 掺杂衬底用作FET的栅极，纳米线的掩蔽掉的部分用作FET的沟道，并且嵌入的SiGe区域用作FET的源极和漏极区域。

公开(公告)号：WO2010016958A1

公开(公告)日：2010-02-11

申请号：PCT/US2009/042065

申请日：2009-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MURRAY, Conal, E. ,  YANG, Chih-Chao

Inventor： MURRAY, Conal, E. ,  YANG, Chih-Chao

IPC: H01L21/70

CPC classification number: H01L21/76849 ,  H01L21/28556 ,  H01L21/28562 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not extend onto an upper surface of a diffusion barrier that separates the at least one conductive material from the dielectric material, and the noble cap material does not deposit on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 200°C or less) chemical deposition process is also provided.

Abstract translation: 提供了一种互连结构，其具有增强的电迁移可靠性，而不降低电路短产量，并且提高了技术可扩展性。 本发明的互连结构包括具有约3.0或更小的介电常数的电介质材料。 电介质材料具有嵌入其中的至少一种导电材料。 贵金属盖直接位于至少一个导电区域的上表面上。 贵金属盖不延伸到扩散阻挡层的上表面，该扩散阻挡层将至少一种导电材料与电介质材料分开，并且贵金属帽材料不会沉积在电介质表面上。 还提供了利用低温（约200℃或更低）化学沉积工艺制造这种互连结构的方法。

公开(公告)号：WO2008082938A2

公开(公告)日：2008-07-10

申请号：PCT/US2007/087766

申请日：2007-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FIORENZA, Giovanni ,  MURRAY, Conal, E. ,  RODBELL, Kenneth, P. ,  TANG, Henry

Inventor： FIORENZA, Giovanni ,  MURRAY, Conal, E. ,  RODBELL, Kenneth, P. ,  TANG, Henry

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/16

Abstract: A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N interconnect layers into multiple pixels, and (iii) determining a first path of the traveling particle in a first interconnect layer of the N interconnect layers, (iv) identifying M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle, M being a positive integer, and (v) determining a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels.

Abstract translation: 确定设计结构相对于行进颗粒的停止力的方法。 该方法包括（i）提供设计结构的设计信息，该设计结构包括后端行层，其包括N个互连层，N为正整数，（ii）将N个互连层的每个互连层划分成多个像素 ，和（iii）确定所述N个互连层的第一互连层中的所述行进粒子的第一路径，（iv）识别所述行进粒子的所述第一路径上的所述第一互连层的所述多个像素的M个路径像素，M 作为正整数，以及（v）确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。