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    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    2.
    发明申请
    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 审中-公开
    具有容错地址和命令总线的高可靠性存储器模块

    公开(公告)号：WO2004090723A2

    公开(公告)日：2004-10-21

    申请号：PCT/GB2004/001593

    申请日：2004-04-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GOWER, Kevin ,  HAZELZET, Bruce ,  KELLOGG, Mark ,  PERLMAN, David

    Inventor： GOWER, Kevin ,  HAZELZET, Bruce ,  KELLOGG, Mark ,  PERLMAN, David

    IPC: G06F11/10

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    3.
    发明申请
    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 审中-公开
    具有容错地址和命令总线的高可靠性存储器模块

    公开(公告)号：WO2004090723A3

    公开(公告)日：2005-05-12

    申请号：PCT/GB2004001593

    申请日：2004-04-13

    Applicant: IBM ,  IBM UK ,  GOWER KEVIN ,  HAZELZET BRUCE ,  KELLOGG MARK ,  PERLMAN DAVID

    Inventor： GOWER KEVIN ,  HAZELZET BRUCE ,  KELLOGG MARK ,  PERLMAN DAVID

    IPC: G01R31/28 ,  G06F11/10 ,  G11C29/00 ,  H05K1/11

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是设置有多个触点的卡，其中一些触点是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和具有纠错码的28位和1至2寄存器 （ECC），奇偶校验，用于通过独立总线读取的多字节故障报告电路和用于确定和报告耦合到服务器的存储器接口芯片和存储器控制器或处理器的可纠正错误和不可校正错误状况的实时错误行， 存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。

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