A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    1.
    发明申请
    A HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 审中-公开
    具有容错地址和命令总线的高可靠性存储器模块

    公开(公告)号:WO2004090723A3

    公开(公告)日:2005-05-12

    申请号:PCT/GB2004001593

    申请日:2004-04-13

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块,用于服务器。 存储器模块是设置有多个触点的卡,其中一些触点是冗余的,多个DRAM,锁相环,2或32K位串行EE PROM和具有纠错码的28位和1至2寄存器 (ECC),奇偶校验,用于通过独立总线读取的多字节故障报告电路和用于确定和报告耦合到服务器的存储器接口芯片和存储器控制器或处理器的可纠正错误和不可校正错误状况的实时错误行, 存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。

Patent Agency Ranking