公开(公告)号：US08183682B2

公开(公告)日：2012-05-22

申请号：US12092126

申请日：2006-10-27

Applicant: Paul Dijkstra ,  Roelf Anco Jacob Groenhuis

Inventor： Paul Dijkstra ,  Roelf Anco Jacob Groenhuis

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of packaging a semiconductor die. The method comprises mounting a semiconductor die to a die attach pad on a carrier and electrically coupling an electrode of the semiconductor die and a contact pad on the carrier with a clip carried by a sacrificial substrate. The method further comprises removing the sacrificial substrate to release the clip. The method may be extended to accommodate a carrier having multiple device regions each with a die attach pad and a contact pad for mounting multiple semiconductor die.

Abstract translation: 一种封装半导体管芯的方法。 该方法包括将半导体管芯安装到载体上的管芯附着焊盘上，并用牺牲基板承载的夹子电连接半导体管芯的电极和载体上的接触焊盘。 该方法还包括去除牺牲基板以释放夹子。 该方法可以被扩展以容纳具有多个器件区域的载体，每个器件区域具有管芯附接焊盘和用于安装多个半导体管芯的接触焊盘。

公开(公告)号：US20080272475A1

公开(公告)日：2008-11-06

申请号：US12092121

申请日：2006-10-27

Applicant: Paul Dijkstra ,  Roelf Anco Jacob Groenhuis

Inventor： Paul Dijkstra ,  Roelf Anco Jacob Groenhuis

IPC: H01L23/20 ,  H01L21/56

CPC classification number: H01L23/055 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

Abstract: A die package (72) for a semiconductor die (20). A plurality of the die packages (72) are formed on a single carrier (10) by applying a body (55) of molding compound across a carrier (10) with an air cavity (70) defined in the molding compound about each of a plurality of device regions (12) of the carrier (10). After a semiconductor die (20) is attached inside the air cavity (70) of each device region (12) and electrically connected with at least one contact pad (14, 16, 18), a cover (68) is applied to close all of the air cavities (70). Following singulation, each semiconductor die (20) is located inside the sealed air cavity (70) of one die package (72). The molding compound of each die package (72) may be locked against movement relative to the device region (12) of the carrier (10) by locking features (30, 38, 48, 50). The locking features (30, 38, 48, 50) may constitute portions of contact pads (14, 16, 18) used to establish electrical communication paths from the semiconductor die (20) to the environment outside of the package (72).

Abstract translation: 一种用于半导体管芯（20）的管芯封装（72）。 多个模具封装（72）通过将模制化合物的主体（55）施加到载体（10）上而形成在单个载体（10）上，空腔（70）限定在模制化合物中， 载体（10）的多个装置区域（12）。 在半导体管芯（20）被安装在每个器件区域（12）的空气腔（70）内并且与至少一个接触焊盘（14,16,18）电连接之后，施加盖子（68）以关闭所有 的空气（70）。 在单片化之后，每个半导体管芯（20）位于一个管芯封装（72）的密封空气腔（70）的内部。 通过锁定特征（30,38,48,50），每个模具包装（72）的模制化合物可被锁定以防止相对于载体（10）的装置区域（12）移动。 锁定特征（30,38,48,50）可以构成用于建立从半导体管芯（20）到封装（72）外部的环境的电连通路径的接触焊盘（14,16,18）的部分。

公开(公告)号：US20080230926A1

公开(公告)日：2008-09-25

申请号：US12092179

申请日：2006-11-03

Applicant: Paul Dijkstra ,  Hans Van Rijckevorsel ,  Roelf Groenhuis

Inventor： Paul Dijkstra ,  Hans Van Rijckevorsel ,  Roelf Groenhuis

IPC: H01L23/485 ,  H01L21/283

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/10719 ,  H05K2201/2081 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An inorganic solder mask (48) for use as a surface treatment in masking a connection conductor (32) of a semi-conductor chip package (10) against solder wetting when mounting the chip package (10) to a printed wiring board (50) or other substrate. The connection conductor (32) is partially covered by a metallization contact (42) formed from a distinct metal. The inorganic solder mask (46) is applied to an exposed portion (44) of the connection conductor (32) not covered by the metallization contact (42). The metallization contact (42) is not coated by the inorganic solder mask (46). The presence of the inorganic solder mask (46) significantly reduces or prevents wetting of the exposed portion (44) when molten solder is present on the connection conductor (32) without affecting the solidified solder layer (48) formed on the metallization contact (42). As a result, an extraneous mass of solder does not solidify on the exposed portion (44) of the connection conductor (32).

Abstract translation: 一种用于在将芯片封装（10）安装到印刷电路板（50）时掩蔽半导体芯片封装（10）的连接导体（32）以防止焊料润湿的表面处理的无机焊接掩模（48） 或其他底物。 连接导体（32）部分地由不同金属形成的金属化接触（42）覆盖。 无机焊接掩模（46）被施加到未被金属化接触（42）覆盖的连接导体（32）的暴露部分（44）。 金属化接触（42）没有被无机焊接掩模（46）涂覆。 当熔融焊料存在于连接导体（32）上时，无机焊料掩模（46）的存在显着地减少或防止了暴露部分（44）的润湿，而不影响形成在金属化接触件（42）上的固化的焊料层（48） ）。 结果，外部质量的焊料在连接导体（32）的暴露部分（44）上不固化。

公开(公告)号：US20080280105A1

公开(公告)日：2008-11-13

申请号：US11628517

申请日：2005-05-27

Applicant: Jan Kloosterman ,  Paul Dijkstra

Inventor： Jan Kloosterman ,  Paul Dijkstra

IPC: B32B3/10 ,  H01L21/302

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T428/24479 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An improved method of etching a structure and a structure etched by the method is disclosed. The bottom side of a leadframe of an IC-package is an example of a structure, which advantageously may be etched with the disclosed method. The method includes the steps of providing an etch mask to the substrate to be etched. The etch mask comprising at least two sub-mask: a first sub-mask covering the area which substantially should remain after the etching process, and a second sub-mask covering an area to be removed in the etching process. The second sub-mask is a sacrificial mask in the form of a grid. The presence of the second sub-mask increases the etching speed in the area covered by it.

Abstract translation: 公开了通过该方法蚀刻结构和蚀刻结构的改进方法。 IC封装的引线框的底侧是结构的示例，其有利地可以利用所公开的方法进行蚀刻。 该方法包括以下步骤：向要蚀刻的衬底提供蚀刻掩模。 所述蚀刻掩模包括至少两个子掩模：覆盖在蚀刻工艺之后基本上应保留的区域的第一子掩模，以及覆盖在蚀刻工艺中待除去区域的第二子掩模。 第二子掩模是栅格形式的牺牲掩模。 第二子掩模的存在增加了其覆盖的区域中的蚀刻速度。

公开(公告)号：US20080277772A1

公开(公告)日：2008-11-13

申请号：US12092126

申请日：2006-10-27

Applicant: Roelf Anco Jacob Groenhuis ,  Paul Dijkstra

Inventor： Roelf Anco Jacob Groenhuis ,  Paul Dijkstra

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of packaging a semiconductor die (20). The method comprises mounting a semiconductor die (20) to a die attach pad (34) on a carrier (10) and electrically coupling an electrode (36) of the semiconductor die (20) and a contact pad (16) on the carrier (10) with a clip (54) carried by a sacrificial substrate (58). The method further comprises removing the sacrificial substrate (58) to release the clip (54). The method may be extended to accommodate a carrier (10) having multiple device regions (12, 13) each with a die attach pad (34) and a contact pad (16) for mounting multiple semiconductor die (20).

Abstract translation: 一种封装半导体管芯（20）的方法。 该方法包括将半导体管芯（20）安装到载体（10）上的管芯安装焊盘（34）上并将半导体管芯（20）的电极（36）和载体上的接触焊盘（16） （54）由牺牲衬底（58）承载。 该方法还包括去除牺牲衬底（58）以释放夹子（54）。 该方法可以被扩展以容纳具有多个器件区域（12,13）的载体（10），每个器件区域具有管芯附接焊盘（34）和用于安装多个半导体管芯（20）的接触焊盘（16）。

公开(公告)号：US20070052097A1

公开(公告)日：2007-03-08

申请号：US10575581

申请日：2004-10-12

Applicant: Cornelis Schriks ,  Paul Dijkstra ,  Peter Wilhelmus Van De Water ,  Roelf Groenhuis ,  Johannus Weekamp

Inventor： Cornelis Schriks ,  Paul Dijkstra ,  Peter Wilhelmus Van De Water ,  Roelf Groenhuis ,  Johannus Weekamp

IPC: H01L23/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68377 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15313 ,  H01L2924/18301 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract translation: 该装置具有载体和电气元件。 载体具有第一和相对侧，并且设置有连接层，中间层和接触垫。 元件存在于第一侧并且耦合到连接层。 它至少部分地被封装延伸到中间层中的图案之间的隔离区域中。 保护层存在于载体的第二侧，其覆盖接触垫和中间层之间的界面。

公开(公告)号：US20120286410A1

公开(公告)日：2012-11-15

申请号：US13294126

申请日：2011-11-10

Applicant: Roelf Anco Jacob GROENHUIS ,  Sven WALCZYK ,  Paul DIJKSTRA ,  Emiel de BRUIN

Inventor： Roelf Anco Jacob GROENHUIS ,  Sven WALCZYK ,  Paul DIJKSTRA ,  Emiel de BRUIN

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49562 ,  H01L23/49548 ,  H01L24/97 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a leadframe portion (10) comprising a recess (14) having a depth substantially equal to the thickness of the discrete semiconductor device (20), wherein a raised portion of the leadframe portion adjacent to said recess defines a first contact area (12); a discrete semiconductor device (20) in said recess, wherein the exposed surface (22) of the discrete semiconductor device defines a second contact area; a protective layer (30) covering the leadframe portion and the a discrete semiconductor device but not the first contact area and the second contact area; and respective plating layers (40) covering the first contact area and the second contact area. A method of manufacturing such a package and a carrier comprising such a package are also disclosed.

Abstract translation: 公开了一种分立半导体器件封装（100），其包括引线框架部分（10），引线框架部分（10）包括具有基本上等于分立半导体器件（20）的厚度的深度的凹槽（14），其中引线框架部分的凸起部分 所述凹部限定第一接触区域（12）; 所述凹部中的分立半导体器件（20），其中所述分立半导体器件的所述暴露表面（22）限定第二接触区域; 覆盖引线框架部分和分立半导体器件而不是第一接触区域和第二接触区域的保护层（30）; 以及覆盖第一接触区域和第二接触区域的各个电镀层（40）。 还公开了制造这种封装的方法和包括这种封装的载体。

公开(公告)号：US08159826B2

公开(公告)日：2012-04-17

申请号：US12092179

申请日：2006-11-03

Applicant: Paul Dijkstra ,  Hans Van Rijckevorsel ,  Roelf Groenhuis

Inventor： Paul Dijkstra ,  Hans Van Rijckevorsel ,  Roelf Groenhuis

IPC: H05K7/00

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/10719 ,  H05K2201/2081 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An inorganic solder mask (48) for use as a surface treatment in masking a connection conductor (32) of a semiconductor chip package (10) against solder wetting when mounting the chip package (10) to a printed wiring board (50) or other substrate. The connection conductor (32) is partially covered by a metallization contact (42) formed from a distinct metal. The inorganic solder mask (46) is applied to an exposed portion (44) of the connection conductor (32) not covered by the metallization contact (42). The metallization contact (42) is not coated by the inorganic solder mask (46). The presence of the inorganic solder mask (46) significantly reduces or prevents wetting of the exposed portion (44) when molten solder is present on the connection conductor (32) without affecting the solidified solder layer (48) formed on the metallization contact (42). As a result, an extraneous mass of solder does not solidify on the exposed portion (44) of the connection conductor (32).

Abstract translation: 一种用于在将芯片封装（10）安装到印刷电路板（50）或其它部件上时，用于掩蔽半导体芯片封装（10）的连接导体（32）以防止焊料润湿的表面处理的无机焊接掩模（48） 基质。 连接导体（32）部分地由不同金属形成的金属化接触（42）覆盖。 无机焊接掩模（46）被施加到未被金属化接触（42）覆盖的连接导体（32）的暴露部分（44）。 金属化接触（42）没有被无机焊接掩模（46）涂覆。 当熔融焊料存在于连接导体（32）上时，无机焊料掩模（46）的存在显着地减少或防止了暴露部分（44）的润湿，而不影响形成在金属化接触件（42）上的固化的焊料层（48） ）。 结果，外部质量的焊料在连接导体（32）的暴露部分（44）上不固化。

公开(公告)号：US07989934B2

公开(公告)日：2011-08-02

申请号：US12526619

申请日：2008-02-11

Applicant: Klaas Heres ,  Paul Dijkstra ,  Maarten Nollen

Inventor： Klaas Heres ,  Paul Dijkstra ,  Maarten Nollen

IPC: H01L23/495

CPC classification number: H01L23/3121 ,  H01L21/4832 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/244 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A carrier (100) for bonding a semiconductor chip (114) onto is provided, wherein the carrier (100) comprises a die pad (101) and a plurality of contact pads (102), wherein each of the plurality of contact pads (102) comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (109), a first buffer layer, and a first conductive layer (108). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer (109) into the first conductive layer (108), and at least two of the contact pads (102) has an ultrafine pitch relative to each other.

Abstract translation: 提供一种用于将半导体芯片（114）接合到其上的载体（100），其中所述载体（100）包括芯片焊盘（101）和多个接触焊盘（102），其中所述多个接触焊盘 ）包括导电多层堆叠，其中所述导电多层堆叠包括表面层（109），第一缓冲层和第一导电层（108）。 此外，第一缓冲层包括适于防止表面层（109）的材料扩散到第一导电层（108）中的材料，并且至少两个接触焊盘（102）相对于彼此具有超细间距 。

公开(公告)号：US20090162791A1

公开(公告)日：2009-06-25

申请号：US12391064

申请日：2009-02-23

Applicant: Cornelis Gerardus SCHRIKS ,  Paul DIJKSTRA ,  Peter Wilhelmus Maria VAN DE WATER ,  Roelf Anco Jacob GROENHUIS ,  Johannus Wilhelmus WEEKAMP

Inventor： Cornelis Gerardus SCHRIKS ,  Paul DIJKSTRA ,  Peter Wilhelmus Maria VAN DE WATER ,  Roelf Anco Jacob GROENHUIS ,  Johannus Wilhelmus WEEKAMP

IPC: G03F7/20

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68377 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15313 ,  H01L2924/18301 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract translation: 该装置具有载体和电气元件。 载体具有第一和相对侧，并且设置有连接层，中间层和接触垫。 元件存在于第一侧并且耦合到连接层。 它至少部分地被封装延伸到中间层中的图案之间的隔离区域中。 保护层存在于载体的第二侧，其覆盖接触垫和中间层之间的界面。