公开(公告)号：WO9711418A3

公开(公告)日：1997-05-09

申请号：PCT/US9611716

申请日：1996-07-15

Applicant: INTEL CORP ,  AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：WO0026742A2

公开(公告)日：2000-05-11

申请号：PCT/US9924362

申请日：1999-10-18

Applicant: INTEL CORP ,  FU JOHN WAI CHEONG ,  MULLA DEAN AHMAD ,  MATHEWS GREGORY S ,  SAILER STUART E ,  SHAW JENG JYE

Inventor： FU JOHN WAI CHEONG ,  MULLA DEAN AHMAD ,  MATHEWS GREGORY S ,  SAILER STUART E ,  SHAW JENG-JYE

IPC: G06F12/08 ,  G06F

CPC classification number: G06F12/0855

Abstract: A method is provided for requesting data from a memory (120). The method includes issuing a plurality of data requests to a data request port for the memory (120). The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory (120), and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory (120). An apparatus includes memory (120) having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory (120). The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory (120).

Abstract translation: 提供一种用于从存储器（120）请求数据的方法。 该方法包括向存储器（120）的数据请求端口发出多个数据请求。 多个数据请求包括至少两个有序数据请求。 所述方法包括确定所述有序数据请求中的较早的一个是否对应于所述存储器（120）中的未命中，以及响应于所述有序数据请求中较早的一个对应于 在记忆中的一个念头（120）。 一种装置包括具有用于接收数据请求的至少一个流水线端口的存储器（120）。 端口适于确定数据请求中的较早有序的数据请求是否对应于存储器（120）中的未命中。 响应于确定早期有序数据请求对应于存储器（120）中的未命中，端口将稍后排序的一个数据请求转换为预取。

公开(公告)号：WO1997011418A2

公开(公告)日：1997-03-27

申请号：PCT/US1996011716

申请日：1996-07-15

Applicant: INTEL CORPORATION ,  AJANOVIC, Jasmin ,  MURDOCH, Robert, N. ,  DOBBINS, Timothy, M. ,  SREENIVAS, Aditya ,  SAILER, Stuart, E. ,  RABE, Jeffrey, L.

Inventor： INTEL CORPORATION

IPC: G06F00/00

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

Abstract translation: 公开了一种用于调节由计算机系统中的处理器在总线上发布的交易的延迟的方法和装置。 总线事务记录器耦合到总线上，处理在总线上发出的事务的编码信号。 当总线上发出待处理的事务请求时，耦合到总线的线路发送指示信号。 当新的待处理事务在总线上等待时，CPU等待时间计时器会重新计算总线上的当前事务。 当等待时间超过预定时间时，CPU等待时间会输出到期信号。 交易处理器单元耦合到总线事务记录器，线路和CPU等待时间计时器。 交易处理器单元在事务处理器接收到指示等待发送在总线上的待处理事务的指示信号时，在总线上发出的交易的编码信号指示发出的交易 总线是延迟的候选者，当CPU等待时间输出到期信号时。