公开(公告)号：WO0041083A3

公开(公告)日：2002-05-16

申请号：PCT/US9930719

申请日：1999-12-21

Applicant: INTEL CORP ,  CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

Inventor： CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362

CPC classification number: G06F13/18

Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.

Abstract translation: 根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控​​制器的计算机系统。 存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。 计算机系统还包括耦合到仲裁单元的第一设备和第二设备。 根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。 此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

公开(公告)号：WO0042594A9

公开(公告)日：2002-03-28

申请号：PCT/US0000776

申请日：2000-01-12

Applicant: INTEL CORP ,  DOYLE PETER ,  SREENIVAS ADITYA

Inventor： DOYLE PETER ,  SREENIVAS ADITYA

IPC: G06T1/60 ,  G06F12/00 ,  G06F12/02 ,  G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G1/16

CPC classification number: G09G5/363 ,  G09G5/393 ,  G09G2360/122

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract translation: 提供了一种用于实现动态显示存储器的方法和装置。 适于中央处理器和存储器之间插入的存储器控​​制中心包括图形存储器控制部件。 图形存储器控制组件确定中央处理器访问的操作数是否是图形操作数。 如果是这样，则图形存储器控制部件将由中央处理器提供的虚拟地址转换成适合于将图形操作数定位在存储器中的系统地址。 在一个实施例中，图形控制组件在存储器中维护图形转换表，并利用图形转换表将虚拟地址转换成系统地址。 此外，在一个实施例中，图形控制部件重新排列图形操作数的地址以优化图形设备的性能存储器访问。

公开(公告)号：WO1997011418A2

公开(公告)日：1997-03-27

申请号：PCT/US1996011716

申请日：1996-07-15

Applicant: INTEL CORPORATION ,  AJANOVIC, Jasmin ,  MURDOCH, Robert, N. ,  DOBBINS, Timothy, M. ,  SREENIVAS, Aditya ,  SAILER, Stuart, E. ,  RABE, Jeffrey, L.

Inventor： INTEL CORPORATION

IPC: G06F00/00

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

Abstract translation: 公开了一种用于调节由计算机系统中的处理器在总线上发布的交易的延迟的方法和装置。 总线事务记录器耦合到总线上，处理在总线上发出的事务的编码信号。 当总线上发出待处理的事务请求时，耦合到总线的线路发送指示信号。 当新的待处理事务在总线上等待时，CPU等待时间计时器会重新计算总线上的当前事务。 当等待时间超过预定时间时，CPU等待时间会输出到期信号。 交易处理器单元耦合到总线事务记录器，线路和CPU等待时间计时器。 交易处理器单元在事务处理器接收到指示等待发送在总线上的待处理事务的指示信号时，在总线上发出的交易的编码信号指示发出的交易 总线是延迟的候选者，当CPU等待时间输出到期信号时。

公开(公告)号：WO9711418A3

公开(公告)日：1997-05-09

申请号：PCT/US9611716

申请日：1996-07-15

Applicant: INTEL CORP ,  AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.