公开(公告)号：US20020078330A1

公开(公告)日：2002-06-20

申请号：US09842312

申请日：2001-04-25

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Andrew C. Sturges ,  Nathan M. Sidwell

IPC: G06F009/00

CPC classification number: G06F9/3804 ,  G06F9/3842

Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Abstract translation: 描述用于执行分支指令的计算机系统和执行分支指令的方法。 两个指令取出器分别从存储器执行的指令序列和从执行的指令序列中的由设置的分支指令识别的目标位置开始的指令序列。 当产生效果分支信号时，接下来执行目标指令，并且获取执行指令的获取器开始获取目标指令。 效果分支信号与设定的分支指令分开产生。 在另一方面，效果分支信号是在执行位于要采用分支的指令序列中的点处的条件效果分支指令时产生的。

公开(公告)号：US20020002657A1

公开(公告)日：2002-01-03

申请号：US09924289

申请日：2001-08-08

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Andrew C. Sturges ,  David May

IPC: G06F012/00

CPC classification number: G06F12/126 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0888

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract translation: 在其中处理器能够执行多个处理的系统中描述了操作高速缓冲存储器的方法，每个处理包括一系列指令。 在该方法中，高速缓冲存储器被分为高速缓存分区，每个高速缓存分区具有多个可寻址存储位置，用于保存高速缓冲存储器中的项目。 分配指示符被分配给每个进程，标识哪个（如果有的话）所述高速缓存分区将用于保存用于执行该进程的项目。 当处理器在执行所述当前进程期间请求来自主存储器的项目并且该项目不被保存在高速缓冲存储器中时，该项目从主存储器中取出并被加载到所识别的高速缓存分区中的多个可寻址存储位置之一中。