公开(公告)号：US20140235016A1

公开(公告)日：2014-08-21

申请号：US14155243

申请日：2014-01-14

Applicant: SIGETRONICS Inc. ,  Electronics and Telecommunications Research Institute

Inventor： Jong-Moon PARK ,  Jin Ho LEE ,  Deok-Ho CHO ,  Kyu-Hwan SHIM

IPC: H01L23/00

CPC classification number: H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05138 ,  H01L2224/05638 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29144 ,  H01L2224/29166 ,  H01L2224/29171 ,  H01L2224/32227 ,  H01L2224/32502 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83805 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01026 ,  H01L2924/01014 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor package, including preparing a die including a first metal layer and a second metal layer which are sequentially stacked on a silicon substrate, preparing a package substrate including a lead frame, and forming an adhesive layer between the lead frame and the first metal layer and attaching the die to the package substrate, wherein the forming of the adhesive layer is performed by eutectic bonding between the silicon substrate and the second metal layer. According to the semiconductor package according to an embodiment of the present invention, an adhesive layer can be easily formed by eutectic bonding without a process of forming a preform.

Abstract translation: 提供一种制造半导体封装的方法，包括制备包括依次层叠在硅衬底上的第一金属层和第二金属层的管芯，制备包括引线框架的封装衬底，以及在引线之间形成粘合剂层 框架和第一金属层并将管芯附接到封装衬底，其中通过硅衬底和第二金属层之间的共晶接合来执行粘合剂层的形成。 根据本发明的实施方式的半导体封装，通过共晶接合可以容易地形成粘合层，而不需要形成预成型体。

公开(公告)号：KR101167530B1

公开(公告)日：2012-07-20

申请号：KR20120001306

申请日：2012-01-05

Applicant: SIGETRONICS INC

Inventor： SHIM KYU HWAN ,  CHO DEOK HO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7802 ,  H01L29/1045 ,  H01L29/1054

Abstract: PURPOSE: A super hetero-junction semiconductor device and a manufacturing method thereof are provided to regularly control impurity concentration filler by minimizing co-doping between p-filler and n-filler due to inter-diffusion. CONSTITUTION: A first conductive type silicon semiconductor substrate doped to high concentration is prepared. A first conductive epitaxial layer is formed at the upper side of the first conductive type silicon semiconductor substrate. A plurality of first conductive type fillers is formed by etching the first conductive epitaxial layer as a predetermined distance. A plurality of second conductive type fillers is composed of a SiGe single epitaxial layer having a single composition or a plurality of SiGe single epitaxial layers having a plurality of compositions in order to prevent co-doping of impurities.

Abstract translation: 目的：提供超异质结半导体器件及其制造方法，以通过最小化由互扩散引起的p-填料和n-填料之间的共掺杂来规则地控制杂质浓度填料。 构成：制备掺杂高浓度的第一导电型硅半导体衬底。 第一导电外延层形成在第一导电型硅半导体衬底的上侧。 通过将第一导电外延层蚀刻为预定距离来形成多个第一导电型填料。 多个第二导电型填料由具有单一组成的SiGe单一外延层或具有多个组成的多个SiGe单一外延层组成，以防止杂质的共掺杂。