公开(公告)号：WO2006125135A1

公开(公告)日：2006-11-23

申请号：PCT/US2006/019371

申请日：2006-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GRECO, Stephen, E. ,  STANDAERT, Theodorus, E.

Inventor： GRECO, Stephen, E. ,  STANDAERT, Theodorus, E.

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed, hi one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit (102) using a dual damascene structure (124) in a first dielectric layer (110), and BEOL wiring over a second circuit (104) using a single damascene via structure (126) in the first dielectric layer (110). Then, simultaneously generating BEOL wiring over the first circuit (102) using a dual damascene structure (220) in a second dielectric layer (150), and BEOL wiring over the second circuit (104) using a single damascene line wire structure (160) in the second dielectric layer (150). The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.

Abstract translation: 公开了在同一半导体产品即晶片或芯片上形成用于不同电路的不同后端线（BEOL）布线的方法。在一个实施例中，该方法包括在第一电路（102）上同时产生BEOL布线 ）在第一介电层（110）中使用双镶嵌结构（124），并且使用在第一介电层（110）中的单个镶嵌通孔结构（126）在第二电路（104）上的BEOL布线。 然后，使用第二电介质层（150）中的双镶嵌结构（220）同时在第一电路（102）上产生BEOL布线，以及使用单个镶嵌线结构（160）在第二电路（104）上方布置BEOL布线， 在第二电介质层（150）中。 单个镶嵌通孔结构的宽度大约是双镶嵌结构的通孔部分的宽度的两倍，并且单镶嵌线结构的宽度大约是双镶嵌结构的线丝部分的宽度的两倍。 还公开了一种用于不同电路的具有不同宽度的BEOL布线的半导体产品。

公开(公告)号：WO2013095779A1

公开(公告)日：2013-06-27

申请号：PCT/US2012/062964

申请日：2012-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BASKER, Veeraraghavan S. ,  BU, Huiming ,  LEOBANDUNG, Effendi ,  STANDAERT, Theodorus E. ,  YAMASHITA, Tenko ,  YEH, Chun-Chen

Inventor： BASKER, Veeraraghavan S. ,  BU, Huiming ,  LEOBANDUNG, Effendi ,  STANDAERT, Theodorus E. ,  YAMASHITA, Tenko ,  YEH, Chun-Chen

IPC: H01L27/088

CPC classification number: H01L29/7843 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

Abstract translation: FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。 一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷 。 然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。 通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。 垂直硅化物提高了耐扩散性。

公开(公告)号：WO2008016740A2

公开(公告)日：2008-02-07

申请号：PCT/US2007/069219

申请日：2007-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STANDAERT, Theodorus, E. ,  DAVIS, Pegeen, M. ,  FITZSIMMONS, John, A. ,  GRECO, Stephen, E. ,  KO, Tze-man ,  LUSTIG, Naftali, E. ,  NICHOLSON, Lee, M. ,  SANKARAN, Sujatha

Inventor： STANDAERT, Theodorus, E. ,  DAVIS, Pegeen, M. ,  FITZSIMMONS, John, A. ,  GRECO, Stephen, E. ,  KO, Tze-man ,  LUSTIG, Naftali, E. ,  NICHOLSON, Lee, M. ,  SANKARAN, Sujatha

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。 还提供了由该方法形成的互连结构。

公开(公告)号：WO2013002902A3

公开(公告)日：2013-04-25

申请号：PCT/US2012037919

申请日：2012-05-15

Applicant: IBM ,  HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  STANDAERT THEODORUS E ,  YAMASHITA TENKO

Inventor： HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  STANDAERT THEODORUS E ,  YAMASHITA TENKO

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate (12) having at least one device region (14) located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region (28) having a spacer (34) located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material (36) is then formed and the sacrificial gate region (28) is removed to form an opening (38) that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate (20) and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region (40) and a drain region (42) in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric (46) and a metal gate (48) are then formed into the extended opening.

Abstract translation: 在一个实施例中，提供了一种方法，其包括提供包括具有位于其中的至少一个器件区域（14）的半导体衬底（12）的结构，以及位于所述至少一个中的所述半导体衬底的上表面上的掺杂半导体层 设备区域。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物（34）的牺牲栅极区域（28）。 然后形成平坦化电介质材料（36），去除牺牲栅极区域（28）以形成露出掺杂半导体层的一部分的开口（38）。 开口延伸到半导体衬底（20）的上表面，然后执行退火，其导致部分地形成源区（40）和漏区（42）的掺杂半导体层的剩余部分的扩散扩散 位于掺杂半导体层的剩余部分下方的半导体衬底。 然后，将高k栅极电介质（46）和金属栅极（48）形成为延伸的开口。

公开(公告)号：WO2010134922A1

公开(公告)日：2010-11-25

申请号：PCT/US2009/044952

申请日：2009-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FILIPPI, Ronald ,  STANDAERT, Theodorus, E. ,  GRUNOW, Stephan ,  SANKARAN, Sujatha ,  CHANDA, Kaushik ,  GAMBINO, Jeffrey, P. ,  SIMON, Andrew, H. ,  HU, Chao-kun ,  BONILLA, Griselda

Inventor： FILIPPI, Ronald ,  STANDAERT, Theodorus, E. ,  GRUNOW, Stephan ,  SANKARAN, Sujatha ,  CHANDA, Kaushik ,  GAMBINO, Jeffrey, P. ,  SIMON, Andrew, H. ,  HU, Chao-kun ,  BONILLA, Griselda

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure for an integrated circuit device includes an elongated metal interconnect layer (106) defined within an insulating layer; a metal cap layer (108) formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer (112) formed on both the metal cap layer (108) and the remaining portions of the metal interconnect layer not having the metal cap layer (108) formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer (108) formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer (106).

Abstract translation: 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层（106）; 金属盖层（108），仅形成在金属互连层的顶表面的一部分上; 以及形成在所述金属覆盖层（108）和所述金属互连层的不具有形成在其上的金属覆盖层（108）的其余部分的电介质盖层（112） 其中不具有形成在其上的金属覆盖层（108）的金属互连层的其余部分容易受到电迁移故障机制的影响，以便于通过施加通过细长金属互连层（106）的电流来编程熔丝结构， 。

公开(公告)号：WO2008016740A3

公开(公告)日：2008-06-26

申请号：PCT/US2007069219

申请日：2007-05-18

Applicant: IBM ,  STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在所述ILD材料中形成一个或多个通孔开口; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬里; 在由所述第一衬里覆盖的所述一个或多个通孔开口中的至少一个的顶部上创建一个或多个沟槽开口; 以及形成覆盖沟槽开口和第一衬里的至少一部分的第二衬里。 还提供了由该方法形成的互连结构。

公开(公告)号：WO2013002902A2

公开(公告)日：2013-01-03

申请号：PCT/US2012/037919

申请日：2012-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HARAN, Balasubramanian ,  CHENG, Kangguo ,  PONOTH, Shom ,  STANDAERT, Theodorus, E. ,  YAMASHITA, Tenko

Inventor： HARAN, Balasubramanian ,  CHENG, Kangguo ,  PONOTH, Shom ,  STANDAERT, Theodorus, E. ,  YAMASHITA, Tenko

CPC classification number: H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate (12) having at least one device region (14) located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region (28) having a spacer (34) located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material (36) is then formed and the sacrificial gate region (28) is removed to form an opening (38) that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate (20) and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region (40) and a drain region (42) in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric (46) and a metal gate (48) are then formed into the extended opening.

Abstract translation: 在一个实施例中，提供了一种方法，该方法包括提供包括半导体衬底（12）的结构，该半导体衬底具有位于其中的至少一个器件区域（14）以及位于半导体衬底 在至少一个器件区域中的半导体衬底。 在提供该结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的隔离物（34）的牺牲栅极区域（28）。 然后形成平面化介电材料（36），并去除牺牲栅极区（28）以形成暴露部分掺杂半导体层的开口（38）。 开口延伸到半导体衬底（20）的上表面，然后执行退火，该退火导致从形成源区（40）和漏区（42）的掺杂半导体层的剩余部分向外扩散掺杂物 位于该掺杂半导体层的其余部分之下的半导体衬底。 然后在延伸的开口中形成高k栅极电介质（46）和金属栅极（48）。

公开(公告)号：WO2006088534A1

公开(公告)日：2006-08-24

申请号：PCT/US2005/043465

申请日：2005-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CLEVENGER, Lawrence, A. ,  DALTON, Timothy, J. ,  HSU, Louis, C. ,  RADENS, Carl, J. ,  STANDAERT, Theodorus, E. ,  WONG, Keith, Kwong, Hon ,  YANG, Chih-Chao

Inventor： CLEVENGER, Lawrence, A. ,  DALTON, Timothy, J. ,  HSU, Louis, C. ,  RADENS, Carl, J. ,  STANDAERT, Theodorus, E. ,  WONG, Keith, Kwong, Hon ,  YANG, Chih-Chao

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.

Abstract translation: 一种制造互连的方法，包括：在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。