公开(公告)号：WO2013095779A1

公开(公告)日：2013-06-27

申请号：PCT/US2012/062964

申请日：2012-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BASKER, Veeraraghavan S. ,  BU, Huiming ,  LEOBANDUNG, Effendi ,  STANDAERT, Theodorus E. ,  YAMASHITA, Tenko ,  YEH, Chun-Chen

Inventor： BASKER, Veeraraghavan S. ,  BU, Huiming ,  LEOBANDUNG, Effendi ,  STANDAERT, Theodorus E. ,  YAMASHITA, Tenko ,  YEH, Chun-Chen

IPC: H01L27/088

CPC classification number: H01L29/7843 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

Abstract translation: FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。 一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷 。 然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。 通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。 垂直硅化物提高了耐扩散性。

公开(公告)号：WO2012094155A1

公开(公告)日：2012-07-12

申请号：PCT/US2011/066466

申请日：2011-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HAENSCH, Wilfried, E-A. ,  KULKARNI, Pranita ,  YAMASHITA, Tenko

Inventor： HAENSCH, Wilfried, E-A. ,  KULKARNI, Pranita ,  YAMASHITA, Tenko

IPC: H01L21/8242

CPC classification number: H01L21/845 ,  H01L27/1211

Abstract: A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.

Abstract translation: 一种结构包括形成第一和至少第二鳍结构。 第一和至少第二鳍结构中的每一个具有垂直取向的半导体本体。 垂直取向的半导体主体由垂直表面组成。 在第一和至少第二鳍结构中的每一个中的掺杂区域包括存在于半导体本体中的掺杂剂离子的浓度，以形成第一电阻器和至少第二电阻器，以及一对合并的翅片，其形成在 第一和至少第二鳍结构的掺杂区域。 一对合并的翅片电连接，使得第一和至少第二电阻器彼此并联电连接。

公开(公告)号：WO2013002902A2

公开(公告)日：2013-01-03

申请号：PCT/US2012/037919

申请日：2012-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HARAN, Balasubramanian ,  CHENG, Kangguo ,  PONOTH, Shom ,  STANDAERT, Theodorus, E. ,  YAMASHITA, Tenko

Inventor： HARAN, Balasubramanian ,  CHENG, Kangguo ,  PONOTH, Shom ,  STANDAERT, Theodorus, E. ,  YAMASHITA, Tenko

CPC classification number: H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate (12) having at least one device region (14) located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region (28) having a spacer (34) located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material (36) is then formed and the sacrificial gate region (28) is removed to form an opening (38) that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate (20) and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region (40) and a drain region (42) in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric (46) and a metal gate (48) are then formed into the extended opening.

Abstract translation: 在一个实施例中，提供了一种方法，该方法包括提供包括半导体衬底（12）的结构，该半导体衬底具有位于其中的至少一个器件区域（14）以及位于半导体衬底 在至少一个器件区域中的半导体衬底。 在提供该结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的隔离物（34）的牺牲栅极区域（28）。 然后形成平面化介电材料（36），并去除牺牲栅极区（28）以形成暴露部分掺杂半导体层的开口（38）。 开口延伸到半导体衬底（20）的上表面，然后执行退火，该退火导致从形成源区（40）和漏区（42）的掺杂半导体层的剩余部分向外扩散掺杂物 位于该掺杂半导体层的其余部分之下的半导体衬底。 然后在延伸的开口中形成高k栅极电介质（46）和金属栅极（48）。

公开(公告)号：WO2013002902A3

公开(公告)日：2013-04-25

申请号：PCT/US2012037919

申请日：2012-05-15

Applicant: IBM ,  HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  STANDAERT THEODORUS E ,  YAMASHITA TENKO

Inventor： HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  STANDAERT THEODORUS E ,  YAMASHITA TENKO

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate (12) having at least one device region (14) located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region (28) having a spacer (34) located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material (36) is then formed and the sacrificial gate region (28) is removed to form an opening (38) that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate (20) and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region (40) and a drain region (42) in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric (46) and a metal gate (48) are then formed into the extended opening.

Abstract translation: 在一个实施例中，提供了一种方法，其包括提供包括具有位于其中的至少一个器件区域（14）的半导体衬底（12）的结构，以及位于所述至少一个中的所述半导体衬底的上表面上的掺杂半导体层 设备区域。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物（34）的牺牲栅极区域（28）。 然后形成平坦化电介质材料（36），去除牺牲栅极区域（28）以形成露出掺杂半导体层的一部分的开口（38）。 开口延伸到半导体衬底（20）的上表面，然后执行退火，其导致部分地形成源区（40）和漏区（42）的掺杂半导体层的剩余部分的扩散扩散 位于掺杂半导体层的剩余部分下方的半导体衬底。 然后，将高k栅极电介质（46）和金属栅极（48）形成为延伸的开口。