公开(公告)号：WO2012012157A2

公开(公告)日：2012-01-26

申请号：PCT/US2011/042296

申请日：2011-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ANDERSON, Frederick, G. ,  LARY, Jenifer, E. ,  RASSEL, Robert, M. ,  STIDHAM, Mark, E.

Inventor： ANDERSON, Frederick, G. ,  LARY, Jenifer, E. ,  RASSEL, Robert, M. ,  STIDHAM, Mark, E.

IPC: H01L29/872 ,  H01L29/47

CPC classification number: H01L29/872 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/66143

Abstract: A Schottky barrier diode comprises a first-type substrate (100), a second-type well isolation region (102) on the first-type substrate, and a first-type well region (110) on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring (106) is on the second-type well isolation region. A second-type well region (104) is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region (108) is on the second-type well region, and a first-type contact region (112) contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer (124) is on the first- type contact region and a second ohmic metallic layer (126) is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.

Abstract translation: 肖特基势垒二极管包括第一类型衬底（100），第一类型衬底上的第二类型阱隔离区（102）和第二类型阱隔离区上的第一类型阱区（110）。 在这里的实施例中，被称为周边电容阱接合环（106）的特征在第二类型的隔离区域上。 第二类型井区域（104）位于第二类型井隔离区域上。 周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。 第二类型接触区域（108）位于第二类型阱区域上，并且第一类型接触区域（112）接触第一类型阱区域的内部部分。 第一类型阱区域的内部位于第一类型接触区域的中心内。 另外，第一欧姆金属层（124）在第一类型接触区域上，第二欧姆金属层（126）位于第一类型阱区域上。 第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。

公开(公告)号：WO2012106101A3

公开(公告)日：2012-10-26

申请号：PCT/US2012021483

申请日：2012-01-17

Applicant: IBM ,  RASSEL ROBERT M ,  STIDHAM MARK E

Inventor： RASSEL ROBERT M ,  STIDHAM MARK E

IPC: H01L29/872 ,  H01L21/328

CPC classification number: H01L29/66143 ,  G06F17/5068 ,  H01L29/872

Abstract: Disclosed are embodiments of a Schottky barrier diode (100). This Schottky barrier diode can be formed in a semiconductor substrate (101) having a doped region (110) with a first conductivity type. A trench isolation structure (120) can laterally surround a section (111) of the doped region at the top surface (102) of the substrate. A semiconductor layer (150) can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion (151) over the defined section (111) of the doped region and a guardring portion (152) over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer (140) can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.

Abstract translation: 公开了肖特基势垒二极管（100）的实施例。 该肖特基势垒二极管可以形成在具有第一导电类型的掺杂区域（110）的半导体衬底（101）中。 沟槽隔离结构（120）可横向地围绕衬底的顶表面（102）处的掺杂区域的部分（111）。 半导体层（150）可以位于衬底的顶表面上。 该半导体层可以在掺杂区域的限定部分（111）上方具有肖特基势垒部分（151），并且在沟槽隔离结构之上的护套部分（152）横向围绕肖特基势垒部分。 肖特基势垒部分可以具有第一导电类型，并且保护部分可以具有不同于第一导电类型的第二导电类型。 金属硅化物层（140）可以覆盖半导体层。 还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

公开(公告)号：WO2012012157A3

公开(公告)日：2012-04-26

申请号：PCT/US2011042296

申请日：2011-06-29

Applicant: IBM ,  ANDERSON FREDERICK G ,  LARY JENIFER E ,  RASSEL ROBERT M ,  STIDHAM MARK E

Inventor： ANDERSON FREDERICK G ,  LARY JENIFER E ,  RASSEL ROBERT M ,  STIDHAM MARK E

IPC: H01L29/872 ,  H01L29/47

CPC classification number: H01L29/872 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/66143

Abstract: A Schottky barrier diode comprises a first-type substrate (100), a second-type well isolation region (102) on the first-type substrate, and a first-type well region (110) on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring (106) is on the second-type well isolation region. A second-type well region (104) is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region (108) is on the second-type well region, and a first-type contact region (112) contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer (124) is on the first- type contact region and a second ohmic metallic layer (126) is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.

Abstract translation: 肖特基势垒二极管包括第一类型衬底（100），在第一类型衬底上的第二类型阱隔离区域（102）以及在第二类型阱隔离区域上的第一类型阱区域（110）。 通过本文的实施例，被称为周边电容阱结环（106）的特征位于第二类型阱隔离区上。 第二类型阱区（104）位于第二类型阱隔离区上。 周边电容阱连接环位于第一类型阱区和第二类型阱区之间并将其隔开。 第二类型接触区域（108）位于第二类型阱区域上，并且第一类型接触区域（112）接触第一类型阱区域的内部部分。 第一类型阱区的内部位于第一类型接触区的中心内。 此外，第一欧姆金属层（124）位于第一型接触区上，而第二欧姆金属层（126）位于第一型阱区上。 第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处与第二欧姆金属层接触。

公开(公告)号：WO2012106101A2

公开(公告)日：2012-08-09

申请号：PCT/US2012/021483

申请日：2012-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RASSEL, Robert, M. ,  STIDHAM, Mark, E.

Inventor： RASSEL, Robert, M. ,  STIDHAM, Mark, E.

IPC: H01L29/872 ,  H01L21/328

CPC classification number: H01L29/66143 ,  G06F17/5068 ,  H01L29/872

Abstract: Disclosed are embodiments of a Schottky barrier diode (100). This Schottky barrier diode can be formed in a semiconductor substrate (101) having a doped region (110) with a first conductivity type. A trench isolation structure (120) can laterally surround a section (111) of the doped region at the top surface (102) of the substrate. A semiconductor layer (150) can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion (151) over the defined section (111) of the doped region and a guardring portion (152) over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer (140) can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.

Abstract translation: 公开了肖特基势垒二极管（100）的实施例。 该肖特基势垒二极管可以形成在具有第一导电类型的掺杂区域（110）的半导体衬底（101）中。 沟槽隔离结构（120）可横向包围衬底的顶表面（102）处的掺杂区域的部分（111）。 半导体层（150）可以位于衬底的顶表面上。 该半导体层可以具有在掺杂区的限定部分（111）上方的肖特基势垒部分（151）和在肖特基势垒部分的侧向包围的沟槽隔离结构上的防护部分（152）。 肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。 金属硅化物层（140）可以覆盖半导体层。 还公开了形成该肖特基势垒二极管的方法和用于肖特基势垒二极管的设计结构的实施例。