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    INTER -DIE INTERCONNECTION INTERFACE
    2.
    发明申请
    INTER -DIE INTERCONNECTION INTERFACE 审中-公开
    互联互连接口

    公开(公告)号：WO2011095963A3

    公开(公告)日：2011-10-06

    申请号：PCT/IB2011051126

    申请日：2011-03-17

    Applicant: STMICROELECTRONICS GRENOBLE2 SAS ,  ST MICROELECTRONICS RES & DEV ,  URZI IGNAZIO ANTONINO ,  D AUDIGIER PHILIPPE ,  SAUVAGE OLIVIER ,  JONES ANDREW MICHAEL ,  RYAN STUART

    Inventor： URZI IGNAZIO ANTONINO ,  D AUDIGIER PHILIPPE ,  SAUVAGE OLIVIER ,  JONES ANDREW MICHAEL ,  RYAN STUART

    IPC: G06F13/38 ,  G06F13/42

    CPC classification number: G06F13/385 ,  G06F13/4265

    Abstract: A die is provided for use in a package comprising said die and at least one further die. The die comprises an interface configured to receive a transaction from the further die via an interconnect and for transmitting a response to the further die via the interconnect. The die also has mapping circuitry configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. The arrangement ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

    Abstract translation: 提供了一种用于包括所述管芯和至少一个另外的管芯的包装的管芯。 芯片包括被配置为经由互连从另外的裸片接收事务并且经由互连发送对另外的管芯的响应的接口。 芯片还具有映射电路，其被配置为向接收的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息之一。 该安排确保用相同的原始源标识和目标标记的事务的顺序，并允许用不同的源标识符标记的事务被无序处理。

    INTER -DIE INTERCONNECTION INTERFACE
    3.
    发明申请
    INTER -DIE INTERCONNECTION INTERFACE 审中-公开
    互联互连接口

    公开(公告)号：WO2011095962A3

    公开(公告)日：2011-10-06

    申请号：PCT/IB2011051124

    申请日：2011-03-17

    Applicant: STMICROELECTRONICS GRENOBLE2 SAS ,  ST MICROELECTRONICS RES & DEV ,  URZI IGNAZIO ANTONINO ,  SAUVAGE OLIVIER ,  D AUDIGIER PHILIPPE ,  JONES ANDREW MICHAEL ,  RYAN STUART

    Inventor： URZI IGNAZIO ANTONINO ,  SAUVAGE OLIVIER ,  D AUDIGIER PHILIPPE ,  JONES ANDREW MICHAEL ,  RYAN STUART

    IPC: G06F13/38 ,  G06F13/42

    CPC classification number: G06F13/4265 ,  G06F13/385

    Abstract: A die for use in a package is provided. The package comprises the die and at least one further die. The die has an interface configured to receive a transaction from the further die via an interconnect and to transmit a response to said transaction to said further die via the interconnect. The die also has mapping circuitry which is configured to receive at least first source identity information of the received transaction, said first source identity information being associated with a source of the transaction. The mapping circuitry is configured to modify the transaction to comprise local source identity information as source identity information for the transaction. The mapping circuitry is configured to modify said received transaction to provide said first source identity information in a further field.

    Abstract translation: 提供用于包装的模具。 该封装包括裸片和至少一个另外的裸片。 管芯具有被配置为经由互连从另外管芯接收事务的接口，并且经由互连将对所述事务的响应发送到所述另外的管芯。 管芯还具有映射电路，其被配置为至少接收所接收的事务的第一源标识信息，所述第一源标识信息与事务的源相关联。 映射电路被配置为修改事务以包括本地源身份信息作为用于事务的源标识信息。 映射电路被配置为修改所述接收到的事务以在另一个字段中提供所述第一源标识信息。

    A DIE
    4.
    发明申请
    A DIE 审中-公开
    一死

    公开(公告)号：WO2011095962A2

    公开(公告)日：2011-08-11

    申请号：PCT/IB2011/051124

    申请日：2011-03-17

    Applicant: STMicroelectronics (Grenoble2) SAS ,  STMicroelectronics (Research & Development) Limited ,  URZI, Ignazio Antonino ,  SAUVAGE, Olivier ,  D'AUDIGIER, Philippe ,  JONES, Andrew Michael ,  RYAN, Stuart

    Inventor： URZI, Ignazio Antonino ,  SAUVAGE, Olivier ,  D'AUDIGIER, Philippe ,  JONES, Andrew Michael ,  RYAN, Stuart

    IPC: G06F13/38

    CPC classification number: G06F13/4265 ,  G06F13/385

    Abstract: A die for use in a package is provided. The package comprises the die and at least one further die. The die has an interface configured to receive a transaction from the further die via an interconnect and to transmit a response to said transaction to said further die via the interconnect. The die also has mapping circuitry which is configured to receive at least first source identity information of the received transaction, said first source identity information being associated with a source of the transaction. The mapping circuitry is configured to modify the transaction to comprise local source identity information as source identity information for the transaction. The mapping circuitry is configured to modify said received transaction to provide said first source identity information in a further field.

    Abstract translation: 提供了一种用于包装的模具。 该封装包括裸片和至少一个另外的裸片。 管芯具有被配置为经由互连从另外管芯接收事务的接口，并且经由互连将对所述事务的响应发送到所述另外的管芯。 芯片还具有映射电路，其被配置为接收所接收的事务的至少第一源标识信息，所述第一源标识信息与事务的源相关联。 映射电路被配置为修改事务以包括本地源身份信息作为用于事务的源标识信息。 映射电路被配置为修改所述接收到的事务以在另一个字段中提供所述第一源标识信息。

    A DIE
    6.
    发明申请
    A DIE 审中-公开
    一死

    公开(公告)号：WO2011095963A2

    公开(公告)日：2011-08-11

    申请号：PCT/IB2011/051126

    申请日：2011-03-17

    Applicant: STMICROELECTRONICS (GRENOBLE2) SAS ,  STMicroelectronics (Research & Development) Limited ,  URZI, Ignazio Antonino ,  D'AUDIGIER, Philippe ,  SAUVAGE, Olivier ,  JONES, Andrew Michael ,  RYAN, Stuart

    Inventor： URZI, Ignazio Antonino ,  D'AUDIGIER, Philippe ,  SAUVAGE, Olivier ,  JONES, Andrew Michael ,  RYAN, Stuart

    IPC: G06F13/38

    CPC classification number: G06F13/385 ,  G06F13/4265

    Abstract: A die is provided for use in a package comprising said die and at least one further die. The die comprises an interface configured to receive a transaction from the further die via an interconnect and for transmitting a response to the further die via the interconnect. The die also has mapping circuitry configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. The arrangement ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

    Abstract translation: 提供了一种用于包括所述管芯和至少一个另外的管芯的包装的管芯。 芯片包括被配置为经由互连从另外的裸片接收事务并且经由互连发送对另外的管芯的响应的接口。 芯片还具有映射电路，其被配置为向接收的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息之一。 该安排确保用相同的原始源标识和目标标记的事务的顺序，并允许用不同的源标识符标记的事务被无序处理。

    Apparatus and methods implementing dispatch mechanisms for offloading executable functions
    10.
    发明专利
    Apparatus and methods implementing dispatch mechanisms for offloading executable functions 未知

    公开(公告)号：GB2546343A

    公开(公告)日：2017-07-19

    申请号：GB201603709

    申请日：2016-03-03

    Applicant: STMICROELECTRONICS (GRENOBLE2) SAS ,  TECH EDUCATIONAL INST OF CRETE

    Inventor： ANTONIO-MARCELLO COPPOLA ,  GEORGIOS KORNAROS ,  MILTOS GRAMMATIKAKIS

    IPC: G06F15/163

    Abstract: A first processor 901 is configured to execute a user-level application that operates in a virtual address space. A co-processor 903 is configured to execute a computing kernel function associated with user-level application elements to be performed on the co-processor. The computing kernel is configured to operate in a virtual address space. A memory 911 has physical addresses, and a partition managed by an OS kernel associated with the first processor and is used to map the virtual address spaces and further associated with the co-processor and suitable for mapping its virtual address space. A packet processor 971, is configured to manage communications between the first processor and the co-processor by receiving at least one packet with memory addresses identifying the code and data of computing kernel from the first processor. The packet is stored in a queue associated with the user level application; and is output to the co-processor, such that the co-processor is enabled to execute the computing kernel. Circular buffers may be used for a packet queue (821, figure 7) and the co-processor may be on-chip.

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