公开(公告)号：US20150046614A1

公开(公告)日：2015-02-12

申请号：US13965020

申请日：2013-08-12

Applicant: Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Francois FOSSE ,  Thierry DELALANDE ,  Ivar HOLAND ,  James HALLMAN

Inventor： Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Francois FOSSE ,  Thierry DELALANDE ,  Ivar HOLAND ,  James HALLMAN

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract translation: 公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。 在一些实现中，PAC存储可以由软件设置或清除的数据。 该数据对应于被路由到对应的外围组件的PAC的输出信号。 当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。 当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

公开(公告)号：US20140215185A1

公开(公告)日：2014-07-31

申请号：US13753380

申请日：2013-01-29

Applicant: Stein Danielsen

Inventor： Stein Danielsen

IPC: G06F9/38

CPC classification number: G06F9/325 ,  G06F9/381 ,  G06F9/3836

Abstract: In one aspect, a processor is configured to store instructions fetched from a program memory in an instruction queue, determine that an instruction to be decoded defines a beginning of a loop routine, and determine whether the instruction is stored in the instruction queue. In response to determining that the instruction is stored in the instruction queue, the processor disables fetching of instructions from the program memory, fetches instructions of the loop routine from the instruction queue, and stores the instructions of the loop routine in an instruction register. In response to determining that the instruction is not stored in the instruction queue, the processor fetches the instruction from the program memory, stores the instruction in the instruction queue, and stores the instruction in the instruction register.

Abstract translation: 一方面，处理器被配置为存储从指令队列中的程序存储器中取出的指令，确定要解码的指令定义循环程序的开始，并且确定指令是否存储在指令队列中。 响应于确定指令存储在指令队列中，处理器禁止从程序存储器中取出指令，从指令队列中取出循环例程的指令，并将循环例程的指令存储在指令寄存器中。 响应于确定指令未被存储在指令队列中，处理器从程序存储器中取出指令，将指令存储在指令队列中，并将该指令存储在指令寄存器中。

公开(公告)号：US08415975B1

公开(公告)日：2013-04-09

申请号：US13304287

申请日：2011-11-23

Applicant: Laurentiu Birsan ,  Stein Danielsen

Inventor： Laurentiu Birsan ,  Stein Danielsen

IPC: H03K19/177

CPC classification number: G06F13/4221 ,  G06F13/00 ,  G06F13/40 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

Abstract: Programmable logic units are described. A described unit includes one or more first logic elements that are individually programmable to be one of a plurality of first functions; one or more second logic elements that are a decoder; one or more third logic elements that are individually programmable to be one of a plurality of second functions; and a programmable interconnect array that selectively forms one or more interconnections within a group including the logic elements, one or more input interfaces, and one or more output interfaces. The array is programmable in routing one or more input signals to at least a portion of the logic elements, routing one or more intermediate signals among at least a portion of the logic elements, and routing one or signals from at least a portion of the logic elements to produce one or more output signals via the output interface.

Abstract translation: 描述可编程逻辑单元。 所描述的单元包括单个可编程为多个第一功能之一的一个或多个第一逻辑元件; 作为解码器的一个或多个第二逻辑元件; 可单独地编程为多个第二功能之一的一个或多个第三逻辑元件; 以及可选择地在包括逻辑元件，一个或多个输入接口以及一个或多个输出接口的组内形成一个或多个互连的可编程互连阵列。 该阵列是可编程的，将一个或多个输入信号路由到至少一部分逻辑元件，在至少一部分逻辑元件之间布线一个或多个中间信号，以及从逻辑的至少一部分路由一个或多个信号 元件通过输出接口产生一个或多个输出信号。

公开(公告)号：US20150046616A1

公开(公告)日：2015-02-12

申请号：US13964971

申请日：2013-08-12

Applicant: Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Thierry DELALANDE ,  Ivar HOLAND ,  Mona OPSAHL

Inventor： Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Thierry DELALANDE ,  Ivar HOLAND ,  Mona OPSAHL

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F13/102 ,  G06F13/14

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract translation: 公开了一种用于访问外围总线上的外设寄存器的灵活宽度外设寄存器映射。