公开(公告)号：US20070033306A1

公开(公告)日：2007-02-08

申请号：US11493360

申请日：2006-07-26

Applicant: Sylvain Garnier ,  Thierry Delalande ,  Laurentiu Birsan

Inventor： Sylvain Garnier ,  Thierry Delalande ,  Laurentiu Birsan

IPC: G06F5/00

CPC classification number: G06F5/10 ,  G06F2205/063 ,  G06F2205/065

Abstract: An interfacing device (23) of the type enabling one-way interfacing between a master unit (21) and a slave unit (22), includes: a memory plane managed according to a “first in, first out” mode, with write and read pointers, and making it possible to store words coming from the master unit, via an input bus (FIFODin); a bank of output registers capable of containing words read in the memory plane and providing an output signal (FIFODout) capable of being read by the slave unit; a mechanism configured to receive read requests (FIFORdRq=1) coming from the slave unit and write requests (FIFOWr=1) coming from the master unit, each read request requiring the reading of a word group. The interfacing device further includes: a mechanism configured to receive, for each read request, of the size (NbWords) of the word group associated with said read request, size being variable from one read request to the other; and a mechanism configured to acknowledge read requests, generating, for each read request, an acknowledgement signal with a “true” value (FIFORdAck=1) if a number of words at least equal to the size (NbWords) of the word group associated with read request is available on the output signal (FIFODout) of the bank of output registers.

Abstract translation: 一种能够在主单元（21）和从单元（22）之间进行单向接口的接口设备（23），包括：根据“先进先出”模式管理的存储器平面，其中写入和 读取指针，并且可以通过输入总线（FIFODin）来存储来自主单元的单词; 输出寄存器组，其能够包含在存储器平面中读取的字，并提供能够由从属单元读取的输出信号（FIFODout）; 一种被配置为接收来自从单元的读取请求（FIFORdRq = 1）并写入来自主单元的请求（FIFOWr = 1）的机制，每个读取请求需要读取单词组。 接口设备还包括：机构，被配置为针对每个读取请求接收与所述读取请求相关联的单词组的大小（NbWords），其大小可从一个读取请求变为另一个; 以及被配置为确认读取请求的机制，如果至少等于与...相关联的单词组的大小（NbWords）的字数，则为每个读取请求生成具有“真实”值（FIFORdAck = 1）的确认信号 在输出寄存器组的输出信号（FIFODout）上可以读取请求。

公开(公告)号：US20150046616A1

公开(公告)日：2015-02-12

申请号：US13964971

申请日：2013-08-12

Applicant: Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Thierry DELALANDE ,  Ivar HOLAND ,  Mona OPSAHL

Inventor： Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Thierry DELALANDE ,  Ivar HOLAND ,  Mona OPSAHL

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F13/102 ,  G06F13/14

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract translation: 公开了一种用于访问外围总线上的外设寄存器的灵活宽度外设寄存器映射。

公开(公告)号：US08902395B2

公开(公告)日：2014-12-02

申请号：US13617125

申请日：2012-09-14

Applicant: Sebastien Jouin ,  Sylvan Garnier ,  Thierry Delalande

Inventor： Sebastien Jouin ,  Sylvan Garnier ,  Thierry Delalande

IPC: G02F1/1345

CPC classification number: G09G3/36 ,  G09G3/3622 ,  G09G2300/0426

Abstract: A microcontroller for controlling a liquid crystal display (LCD) is mountable in any one of multiple package types. The microcontroller includes a LCD controller to generate logical mapping signals indicative of voltages to be applied to segment terminals of a LCD glass. A driver circuit drives the segment terminals selectively. A remapping unit receives the logical mapping signals from the LCD controller and maps the logical mapping signals, for each of the package types, to physical segment terminal drivers in the driver circuit based on a distribution of I/O terminals that are bonded for each package type when that package type is used with the LCD glass.

Abstract translation: 用于控制液晶显示器（LCD）的微控制器可安装在多种封装类型中的任何一种中。 微控制器包括LCD控制器，用于产生指示施加到LCD玻璃的分段端子的电压的逻辑映射信号。 驱动电路选择性地驱动段终端。 重映射单元接收来自LCD控制器的逻辑映射信号，并且基于每个封装结合的I / O端子的分布，将用于每个封装类型的逻辑映射信号映射到驱动器电路中的物理段终端驱动器 当LCD显示屏使用该包装类型时键入。

公开(公告)号：US07411913B2

公开(公告)日：2008-08-12

申请号：US11039175

申请日：2005-01-19

Applicant: Laurentiu Birsan ,  Marc Laurent ,  Thierry Delalande ,  Jean-Sebastien Berthy

Inventor： Laurentiu Birsan ,  Marc Laurent ,  Thierry Delalande ,  Jean-Sebastien Berthy

IPC: G01R31/08

CPC classification number: H04L12/4135 ,  H04L41/082 ,  H04L41/0869 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A process for automatically detecting and configuring with the throughput of a network, in which a device: (a) goes into a listen mode; (b) obtains a triplet of successive transitions in a transmitted signal, the triplet delimiting first and second signal levels, one dominant and the other recessive; (c) measures the duration of each of the first and second levels; (d) as a function of the measured durations, obtains a new throughput configuration by determining values for parameters that define a bit length LBIT; (e) validates the new throughput configuration; (g) if at least one throughput adaptation condition is verified, goes into a normal mode, otherwise obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, then measures the duration of the new level and reiterates steps (d) to (g) taking account of the new signal level.

Abstract translation: 一种用于以网络的吞吐量自动检测和配置的过程，其中设备：（a）进入监听模式; （b）在发射信号中获得三次连续的转变，三重态限定第一和第二信号电平，一个占优势和另一个隐性; （c）衡量第一和第二级别的持续时间; （d）作为测量持续时间的函数，通过确定定义位长度LIT的参数的值来获得新的吞吐量配置; （e）验证新的吞吐量配置; （g）如果验证了至少一个吞吐量适配条件，则进入正常模式，否则获得信号的下一个转换，该信号的最后一个转换定义为信号的新电平，然后测量新电平的持续时间 并重新考虑新的信号电平的步骤（d）至（g）。

公开(公告)号：US20070255911A1

公开(公告)日：2007-11-01

申请号：US11728198

申请日：2007-03-23

Applicant: Sylvain Garnier ,  Thierry Delalande ,  Laurentiu Birsan

Inventor： Sylvain Garnier ,  Thierry Delalande ,  Laurentiu Birsan

IPC: G06F13/00

CPC classification number: G06F8/4434

Abstract: A method for optimising writing by a master block into an interfacing device between the master block and a slave block. The method includes a step for transformation of a code into assembler language, done before the code in machine language is obtained and including the following steps: transformation of all static unit writes comprising more than one word from the assembler language code into one-word static unit writes; search for each set of N successive static one-word unit writes; replace at least one set of N successive static one-word unit writes by one static unit N-word write of, in the assembler language code, where N is an integer greater than or equal to 2.

Abstract translation: 一种用于优化由主块写入到主块和从块之间的接口装置的方法。 该方法包括将代码转换为汇编语言的步骤，在获得机器语言的代码之前完成，包括以下步骤：将包含来自汇编语言代码的多个单词的所有静态单元写入转换为单字静态 单位写 搜索每组N个连续静态单字单元写入; 在汇编语言代码中，通过一个静态单元替换至少一组N个连续静态单字单元写入，其中N是大于或等于2的整数。

公开(公告)号：US20150046614A1

公开(公告)日：2015-02-12

申请号：US13965020

申请日：2013-08-12

Applicant: Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Francois FOSSE ,  Thierry DELALANDE ,  Ivar HOLAND ,  James HALLMAN

Inventor： Frode Milch PEDERSEN ,  Sebastien JOUIN ,  Stein DANIELSEN ,  Francois FOSSE ,  Thierry DELALANDE ,  Ivar HOLAND ,  James HALLMAN

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract translation: 公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。 在一些实现中，PAC存储可以由软件设置或清除的数据。 该数据对应于被路由到对应的外围组件的PAC的输出信号。 当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。 当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

公开(公告)号：US20140089537A1

公开(公告)日：2014-03-27

申请号：US13692531

申请日：2012-12-03

Applicant: Sebastien Jouin ,  Sylvain Garnier ,  Thierry Delalande ,  Romain Oddoart

Inventor： Sebastien Jouin ,  Sylvain Garnier ,  Thierry Delalande ,  Romain Oddoart

IPC: G06F13/32

CPC classification number: G06F13/32 ,  G06F13/4234 ,  G09G3/36

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract translation: 一种设备包括中央处理单元（CPU），被配置为用于控制数字显示器的显示控制器和被配置为存储对应于数字显示器的数据的存储器。 该设备包括直接存储器访问（DMA）控制器，其被配置为在没有CPU干预的情况下将数据从存储器自动地直接传送到显示控制器。

公开(公告)号：US20140078427A1

公开(公告)日：2014-03-20

申请号：US13617125

申请日：2012-09-14

Applicant: Sebastien Jouin ,  Sylvan Garnier ,  Thierry Delalande

Inventor： Sebastien Jouin ,  Sylvan Garnier ,  Thierry Delalande

IPC: G02F1/133

CPC classification number: G09G3/36 ,  G09G3/3622 ,  G09G2300/0426

Abstract: A microcontroller for controlling a liquid crystal display (LCD) is mountable in any one of multiple package types. The microcontroller includes a LCD controller to generate logical mapping signals indicative of voltages to be applied to segment terminals of a LCD glass. A driver circuit drives the segment terminals selectively. A remapping unit receives the logical mapping signals from the LCD controller and maps the logical mapping signals, for each of the package types, to physical segment terminal drivers in the driver circuit based on a distribution of I/O terminals that are bonded for each package type when that package type is used with the LCD glass.

Abstract translation: 用于控制液晶显示器（LCD）的微控制器可安装在多种封装类型中的任何一种中。 微控制器包括LCD控制器，用于产生指示施加到LCD玻璃的分段端子的电压的逻辑映射信号。 驱动电路选择性地驱动段终端。 重映射单元接收来自LCD控制器的逻辑映射信号，并且基于每个封装结合的I / O端子的分布，将用于每个封装类型的逻辑映射信号映射到驱动器电路中的物理段终端驱动器 当LCD显示屏使用该包装类型时键入。

公开(公告)号：US20050180442A1

公开(公告)日：2005-08-18

申请号：US11039175

申请日：2005-01-19

Applicant: Laurentiu Birsan ,  Marc Laurent ,  Thierry Delalande ,  Jean-Sebastien Berthy

Inventor： Laurentiu Birsan ,  Marc Laurent ,  Thierry Delalande ,  Jean-Sebastien Berthy

IPC: H04L12/24 ,  H04L12/40 ,  H04L12/28

CPC classification number: H04L12/4135 ,  H04L41/082 ,  H04L41/0869 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A process for automatically detecting throughput of a network by a device. The network transmits a signal on which messages are carried that include bits of length LBIT and of a dominant or recessive type. The process includes the following successive steps: (a) the device goes into a listen mode; (b) the device obtains a triplet of successive transitions in the signal transmitted on the network, the triplet delimiting a first and second signal level, one dominant and the other recessive; (c) the device measures the duration, expressed as a period TH number of a clock of the device, of each of the first and second levels; (d) as a function of the measured durations of the signal levels, the device obtains a new throughput configuration by determining values for parameters that define the bit length LBIT; (e) the device validates the new throughput configuration; (g) if the device detects that at least one throughput adaptation condition is verified, it goes into a normal mode, otherwise it obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, it measures the duration of the new level and it reiterates steps (d) to (g) taking account of the new signal level.

Abstract translation: 用于自动检测设备的网络吞吐量的过程。 网络传送信号，其上携带有包括长度为L / BIT的位和具有显性或隐性类型的位的消息。 该过程包括以下连续步骤：（a）设备进入监听模式; （b）该设备获得在网络上发送的信号中的连续转换的三元组，三重态限定第一和第二信号电平，一个占优势和另一个隐性; （c）所述装置测量所述第一和第二电平中的每一个的所述持续时间，表示为所述装置的时钟的周期T H SUB数; （d）根据测量的信号电平持续时间的函数，器件通过确定定义位长度LIT的参数的值来获得新的吞吐量配置; （e）设备验证新的吞吐量配置; （g）如果设备检测到至少一个吞吐量适应条件被验证，则其进入正常模式，否则它获得信号的下一个转换，该信号的定义与上一次转换一个新的信号水平，其测量 新级别的持续时间，并重申步骤（d）至（g），考虑到新的信号水平。