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    IMPROVEMENTS IN OR RELATING TO FIELD MEMORIES
    1.
    发明申请
    IMPROVEMENTS IN OR RELATING TO FIELD MEMORIES 审中-公开
    对现场记忆的改善或相关

    公开(公告)号：WO1995016266A1

    公开(公告)日：1995-06-15

    申请号：PCT/EP1994004071

    申请日：1994-12-07

    Applicant: TEXAS INSTRUMENTS ITALIA SPA ,  TEXAS INSTRUMENTS INCORPORATED ,  IMONDI, Giuliano ,  MENICHELLI, Stefano ,  SANSONE, Carlo

    Inventor： TEXAS INSTRUMENTS ITALIA SPA ,  TEXAS INSTRUMENTS INCORPORATED

    IPC: G11C07/00

    CPC classification number: G11C7/1039

    Abstract: A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word. The distributed architecture improves the transfer of data between the input/output buffers and the internal registers of the memory. A data cache and an improved input erasable realisation are also disclosed.

    Abstract translation: 公开了具有分布式架构的场存储器，特别是以块为单位布置的存储器，其中每个块存储所述字的位或位，所述位在所述字内具有预定位置。 分布式架构改善了输入/输出缓冲器和存储器的内部寄存器之间的数据传输。 还公开了数据高速缓存和改进的输入可擦除实现。

    Improvements in or relating to memories and their manufacture.
    2.
    发明公开
    Improvements in or relating to memories and their manufacture. 失效
    改进的存储和他们的准备。

    公开(公告)号：EP0620524A3

    公开(公告)日：1998-08-12

    申请号：EP94301771

    申请日：1994-03-11

    Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS ITALIA SPA

    Inventor： DI ZENZO MAURIZIO ,  PISTILLI PASQUALE ,  SALSANO ADELLO

    IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  G11C29/00 ,  G11C29/44 ,  G06F11/00

    CPC classification number: G11C29/44 ,  G06F11/1012 ,  G11C5/04 ,  G11C29/88 ,  G11C2029/4402

    Abstract: Subject-matter of this invention is a system for use of semiconductor dynamic memories having faulty locations, wherein such memories are preliminarily organized as memory banks in order to form an elementary information word and subsequently all homologous address locations which contain errors are identified so as to obtain a map which is stored in a not-volatile memory (OTP) associated to the memory banks, thereby creating a transcoding table: and wherein the external user who desires to retrieve the data contained in the memory blocks will have access to said not-volatile memory (OTP) by using successive memory (logic) addresses supplied by an intelligent section of the system and will receive (material) transcoded addressed therefrom, which will enable him to have direct and immediate access to said memory blocks.
    In the system according to this invention, aiming at increasing the number of locations wherein it is possible to store information, by using also somewhat faulty regions, techniques designed for application to error correction are exploited.

    4.
    发明专利
    未知

    公开(公告)号：DE69720126D1

    公开(公告)日：2003-04-30

    申请号：DE69720126

    申请日：1997-09-10

    Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS ITALIA SPA

    Inventor： MENICHELLI STEFANO ,  VALI TOMMASO

    IPC: G11C16/06 ,  G11C8/08 ,  G11C16/12 ,  H03K19/0185 ,  G11C8/00

    Abstract: A voltage translator circuit for driving the rows or wordlines of Flash EEPROM memories, said translator circuit being arranged for receiving control logic voltages in the range 0 to 3.3 volts, and operating voltages for performing reading, programming or erasing operations in the range -9 to 12 volts, said translator circuit comprising a decode section having a NOR gate circuit connected to an inverter circuit (BUFF) through an input node (node 5) to couple a selection signal thereto, wherein: the wordline to be driven (node 1) is connected to ground (VXGND) through a first N-MOS type switch transistor (pull-down 2) the gate of which (node 0) is driven by a selection logic signal applied through said NOR gate and connected to the operation voltage (VX) through a second P-MOS type switch transistor (pull-up 3), a first P-MOS type feedback transistor (TP4), having a gate (node 6) directly driven by said wordline, said first feedback transistor being inserted between the operation voltage (VX) and the gate region (node 6) of said second switch transistor (pull-up 3), a second N-MOS type feedback transistor (TN3), having a gate directly driven by said wordline (node 18), said second feedback transistor being inserted between the connection node (node 6) between said first feedback transistor (TP4) and the gate region of said second switch transistor (pull-up 3) and the input node (node 0) on the gate of said first switch transistor (pull-down 2).

    6.
    发明专利
    未知

    公开(公告)号：DE69526285T2

    公开(公告)日：2002-10-31

    申请号：DE69526285

    申请日：1995-05-26

    Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS ITALIA SPA

    Inventor： GALLO GIROLAMO ,  LATTARO CRISTINA ,  SAVARESE GIUSEPPE

    IPC: G06K9/46 ,  G06K9/62 ,  G06K9/64

    Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological, vector dimension features and the microfeatures of the character are extracted from the character, then the features of the character are compared with a set of reference features corresponding thereto stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character. The relative weighting of the feature can be varied for different types of script or confusing characters to enable still more accurate recognition.

    8.
    发明专利
    未知

    公开(公告)号：DE69423113D1

    公开(公告)日：2000-03-30

    申请号：DE69423113

    申请日：1994-12-07

    Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS ITALIA SPA

    Inventor： IMONDI GIULIANO ,  MENICHELLI STEFANO ,  SANSONE CARLO

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/409

    Abstract: A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word. The distributed architecture improves the transfer of data between the input/output buffers and the internal registers of the memory. A data cache and an improved input erasable realisation are also disclosed.

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