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    3.
    发明专利
    未知

    公开(公告)号：IT1244911B

    公开(公告)日：1994-09-13

    申请号：ITRM910076

    申请日：1991-01-31

    Applicant: TEXAS INSTRUMENTS ITALIA SPA

    Inventor： IMONDI GIULIANO ,  MAROTTA GIULIO ,  PORROVECCHIO GIULIO ,  SAVARESE GIUSEPPE

    IPC: G06N3/063 ,  G06F

    Abstract: Data processing system implementing architecture of a neural network which is subject to a learning process, wherein the data processing system includes n*n synapses arranged in an array of j rows and i columns. A plurality of operational amplifiers respectively corresponding to the rows of the array are provided, with each operational amplifier defining a neuron. The input terminals of all of the synapses arranged in a respective column of the array are connected together and define n inputs of the neural network. The output terminals of the synapses arranged in a respective row of the array are connected together and serve as the inputs to a corresponding one of the plurality of operational amplifiers. Each synapse includes a capacitor connected between ground potential and the input terminal for weighting the synapse by storing a weighting voltage applied thereto. A random access memory has digitally stored voltage values for weighting all of the synapses. A plurality of digital-analog converters, one for each column of the array of synapses, are connected to the random access memory for converting the digital voltage values for weighting the synapses into analog voltage values. The digital-analog converters provide respective outputs to the weighting terminals of the synapses of a column via respective electronic switches for each synapse. Each row of the array includes a bistable circuit for driving the respective electronic switches under the control of a control section which also provides function commands and data to the random access memory.

    5.
    发明专利
    未知

    公开(公告)号：ITRM910077D0

    公开(公告)日：1991-01-31

    申请号：ITRM910077

    申请日：1991-01-31

    Applicant: TEXAS INSTRUMENTS ITALIA SPA

    Inventor： IMONDI GIULIANO ,  MAROTTA GIULIO ,  PORROVECCHIO GIULIO ,  SAVARESE GIUSEPPE

    IPC: A43B5/02 ,  G06N3/063

    Abstract: The subject of the invention is a learning system for a neural net physically insertable in the learning process, which comprises a detecting member for presenting to said neural net the basic information set that said neural net has to learn in order to provide a desired response; a microprocessor suitable to iteratively execute a learning algorithm based on a comparison among said basic information set itself, the response that the neural net provides and the response that one wants to obtain from the neural net (see FIG. 1).

    8.
    发明专利
    未知

    公开(公告)号：IT1265673B1

    公开(公告)日：1996-11-22

    申请号：ITRM930179

    申请日：1993-03-22

    Applicant: TEXAS INSTRUMENTS ITALIA SPA

    Inventor： GALLO GIROLAMO ,  LATTARO CRISTINA ,  LUCENTINI FLAVIO ,  MAROTTA GIULIO ,  SAVARESE GIUSEPPE

    IPC: G06K9/62 ,  G06K9/50 ,  G06K9/64 ,  G06K9/68

    Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological vector features of the character are extracted from the character, then the topological and vector features of the character are compared with a set of reference topological and vector features stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character. The relative weighting of the topological effect and the vector effect can be varied for different types of script to enable still more accurate recognition.

    Memory card with capacitive coupling and interface circuit to be used in it and in co-operation with it
    9.
    发明专利
    Memory card with capacitive coupling and interface circuit to be used in it and in co-operation with it 未知

    公开(公告)号：IT1250970B

    公开(公告)日：1995-04-24

    申请号：ITRM910957

    申请日：1991-12-19

    Applicant: TEXAS INSTRUMENTS ITALIA SPA

    Inventor： MAROTTA GIULIO ,  PINNAVAIA GIUSEPPE

    IPC: G06F20060101 ,  G06F

    Abstract: The subject of the invention is a memory card comprising a small number of resistive contacts for the application of dc voltages and the clock signal, as well as a plurality of capacitor plates to which go a similar plurality of interface circuits, which plates and which interface circuits co-operate with an identical plurality of mirror-image capacitor plates and interface circuits provided in the card driver associated with the apparatus with which the memory card is to be used. The interface circuits comprise a receiving-transmitting assembly RXTX, followed by a demodulation assembly consisting of two demodulator circuits in parallel DEMOD, DEMODB, with the outputs combined in an OR arrangement via a NOR gate circuit NOR1 and an attached inverter circuit INV6. (Figure 1)

    Circuit for selectively deleting a single line of memory in flash EEPROM devices in standard CMOS technology
    10.
    发明专利
    Circuit for selectively deleting a single line of memory in flash EEPROM devices in standard CMOS technology 未知

    公开(公告)号：IT1244917B

    公开(公告)日：1994-09-13

    申请号：ITRM910088

    申请日：1991-02-06

    Applicant: TEXAS INSTRUMENTS ITALIA SPA

    Inventor： GALLO GIROLAMO ,  IMONDI GIULIANO ,  MAROTTA GIULIO

    IPC: G11C20060101 ,  G11C

    Abstract: The subject of the invention is a circuit for selectively deleting a single line of memory in flash EEPROM devices in standard CMOS technology comprising as fundamental component: - a piloting circuit associated with each line of memory, consisting of two level variator circuits inter- cooperating and connected to the line or wordline of the memory through a first output circuit and, respectively, a bootstrap circuit and a second output circuit for carrying out not only the usual reading, programming and deleting functions, but also the selective deletion of the line it is connected to. The following, common to all the lines of memory, are associated with the line piloting circuit: - a control logic to generate the sequence of line piloting circuit selection and control signals; - four load pumps for supplying the various positive and negative voltages for programming and the global and selective or auxiliary deletion; - analogue circuitry for supplying the reference voltages.

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