公开(公告)号：JPH09261040A

公开(公告)日：1997-10-03

申请号：JP26214696

申请日：1996-10-02

Applicant: XILINX INC

Inventor： UIRIAMU ESU KAATAA ,  ROSU EICHI FURIIMAN

IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic circuit formed on an integrated circuit chip in which a desired logic function is realized easily by the user through programming. SOLUTION: This logic device is provided with plural logic elements LEs each of which has an input lead (in) and an output lead (out), and a desired logic form is set to each logic element to realize a desired logic function. A group of interconnection lines L interconnecting the logic elements are provided and plural input/output ports I/O are provided. A programmable connection means is provided to allow a group of the interconnection lines to be mutually connected, to allow a group of the interconnection lines to be connected to input leads or output leads of selected logic elements and to allow a group of interconnection lines to be selectively connected to input/output ports through programming.

公开(公告)号：JPH08307245A

公开(公告)日：1996-11-22

申请号：JP10195896

申请日：1996-04-01

Applicant: XILINX INC

Inventor： NIKORASU KUCHIYAREFUSUKII JIYU ,  DEIBUITSUDO CHIYAN ,  JIESHII ETSUCHI JIENKINSU FUOO

IPC: H03K19/177 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To reduce the area of interconnecting wiring by providing a first circuit containing first and second conductors connected with each other in a programmable form, a second circuit containing similarly connected third and fourth conductors, and a plurality of third circuits. SOLUTION: MUX-based circuits 220(2) are connected between the input terminal 101 and first input line of each two-input MUX 230 and cross-point circuits 210(2) are connected between the I/O terminals 102 and second input lines 110(2) of each MUX 230. Therefore, each MUX 230 is connected to one of functional blocks 110(2) through a line 103. Each MUX 230 is programmed so as to send logical signals from the circuits 210(2) or circuits 220(2) to a related functional block input line 103 through its own programmable selection element 231. The circuits 210(2) contain four longitudinal conductors 211 respectively connected to an I/O terminal 102 through an inverter 212.

公开(公告)号：JPH08263984A

公开(公告)日：1996-10-11

申请号：JP4425096

申请日：1996-02-06

Applicant: XILINX INC

Inventor： FUIRITSUPU EMU FUREIDEIN ,  EDOMONDO WAI CHIYUN ,  CHIYAARUZU AARU ERIKUSON ,  TSUNNRU SHIYUU

IPC: G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  H03K19/173 ,  H03K19/177

Abstract: PROBLEM TO BE SOLVED: To eliminate the need for an undesirable latch time due to a delay in a signal path by using one ridge of a clock signal to trigger a latch operation of an address signal and a data signal relating to function generators. SOLUTION: An address decoder 305A applies a signal to a read address terminal of a function generator 301 and a multiplexer 306A. An address decoder 305B applies a signal to a read address terminal of a function generator 302 and the multiplexer 306A. The multiplexer 306A applies its output signal to a D input terminal of a latch 304A that applies its output to a write address terminal of the function generator 301 in a through-state. The latch 304A is made up of pass transistors(TRs), that is, which stores tentatively the signal to a gate capacitance of an inverter 312. The latch 304A has lots of modifications.

公开(公告)号：JPH07142995A

公开(公告)日：1995-06-02

申请号：JP14129594

申请日：1994-05-30

Applicant: XILINX INC

Inventor： EFU ERITSUKU GETEINGU ,  DEIBITSUDO PII SHIYURUTSU

IPC: H03K19/173 ,  H03K19/00 ,  H03K19/0948

Abstract: PURPOSE: To reduce the entire power consumption of an integrated circuit device by reducing the power consumption of a CMOS inverter in the case of providing an output without inverting an input signal when the input signal of the CMOS inverter is switched. CONSTITUTION: The inverter consists of a P-channel transistor(TR) T1 having a source, a drain and a gate with a high threshold voltage, an N-channel TR T2 having a source, a drain and a gate, an input signal line IN, an output signal line OUT, and a means that applies a positive voltage to the source of the P-channel TR and a negative voltage to the source of the N-channel TR in an inverting mode, and applies a negative voltage to the source of the P-channel TR and a positive voltage to the source of the N-channel TR in a noninverting mode.

公开(公告)号：JPH06283996A

公开(公告)日：1994-10-07

申请号：JP41789290

申请日：1990-12-19

Applicant: XILINX INC

Inventor： ROSU EICHI FURIIMAN

IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

Abstract: PURPOSE: To provide the special interconnection circuit that interconnects selected CLEs in the CLA so as to decrease number of general interconnection components in use. CONSTITUTION: The configuration adaptive logic array has a plurality of configuration adaptive logic elements 40 interconnected variably in response to a control signal to execute a selected logic function. Each configuration adaptive logic element in the array executes any of a plurality of logic functions according to control information set in the element. The function of each configuration adaptive logic element is changed even after being installed in a system by revising the control information set to the element. A configuration that stores control information to provide access to control information stored in each element is provided to properly allow each configuration adaptive logic element to conduct configuration adaptation before start of an operation of the system where the array is one component, and a new interconnection configuration s provided to facilitate the configuration adaptation by each logic element.

公开(公告)号：JPH0224897A

公开(公告)日：1990-01-26

申请号：JP9170389

申请日：1989-04-11

Applicant: XILINX INC

Inventor： HANGU CHIENGU SHII

IPC: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

Abstract: PURPOSE: To improve usability by connecting the output of a first inverter to the input of a second inverter and the output of this second inverter to the input of this first inverter, respectively, and disposing a single gate transistor between the first inverter and a bit line. CONSTITUTION: This memory circuit is provided with the first and second inverters INV1 and INV2 . The output of the inverter INV1 is connected to the input of the inverter INV2 . The output of the inverter INV2 is connected to the input of the inverter INV1 . The single gate transistor TR is connected between the input of the inverter INV1 and the single bit line. The channel size of the gate TR with respect to the channel size of N and P channel TRs is so determined that the trigger voltage of the inverter INV1 is lower than the value obtd. by subtracting the threshold voltage value by a body effect from the voltage applied on the gate of the gate TR at the time of writing and that the writing to a memory cell is executed with high reliability. The reading and writing are well executed by using the single data line in such a manner.

公开(公告)号：JPS62117192A

公开(公告)日：1987-05-28

申请号：JP21559186

申请日：1986-09-12

Applicant: Xilinx Inc

Inventor： HSIEH HUNG-CHENG

IPC: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

CPC classification number: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

公开(公告)号：JP2014103702A

公开(公告)日：2014-06-05

申请号：JP2014050089

申请日：2014-03-13

Applicant: Xilinx Inc ,  ザイリンクス インコーポレイテッドXilinx Incorporated

Inventor： CHRISTOPHER H DICK

IPC: H04J11/00

CPC classification number: H04L5/003 ,  H04L5/0001 ,  H04L27/262

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for carrying spread code information to a receiver without producing a data speed loss.SOLUTION: A method for communicating a data value and a pilot tone in a communication subcarrier in the same communication channel is provided. A first reference phase corresponding to a first data value is selected (810). A pilot tone having the first reference phase is generated (1414). The generated pilot tone (812) is transmitted (1418). The transmitted pilot tone is received (1426). The phase of the received pilot tone is determined (814). From the received pilot tone phase, a second data value is determined (816). The second data value (802) is stored in an electronic storage medium.

Abstract translation: 要解决的问题：提供一种用于在不产生数据速度损失的情况下向接收机传送扩展码信息的方法和电路。解决方案：在同一通信信道中在通信副载波中传送数据值和导频音的方法是 提供。 选择对应于第一数据值的第一参考相位（810）。 产生具有第一参考相位的导频音（1414）。 产生的导频音（812）被发送（1418）。 接收发送的导频音（1426）。 确定接收导频音的相位（814）。 从接收到的导频音阶段，确定第二数据值（816）。 第二数据值（802）被存储在电子存储介质中。

公开(公告)号：JPH09261039A

公开(公告)日：1997-10-03

申请号：JP26212796

申请日：1996-10-02

Applicant: XILINX INC

Inventor： UIRIAMU ESU KAATAA ,  ROSU EICHI FURIIMAN

IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

Abstract: PROBLEM TO BE SOLVED: To allow a user to easily program, so as to realize a desired logical function by providing a means connecting input and output leads to mutual connection lines by respective programming and a means mutually connecting the mutual connecting lines by programming. SOLUTION: Each CLE of nine CLEs 40-1 to 40-9 is provided with plural input leads and not less than one output lead. Each input lead is provided with plural access connection parts and each of them connects a selected general connection lead to an input lead. These logical elements 40-1 to 40-9 are arranged on an integrated circuit chip with a general mutual connection constituting body provided with a programmable access connection part and a programmable general mutual connection part for connecting a general mutual connection lead and various leads to another lead. Then an electrical path from the output lead of one CLE to the input lead of another CLE involves the general mutual connection part.

公开(公告)号：JPH08204543A

公开(公告)日：1996-08-09

申请号：JP12105895

申请日：1995-05-19

Applicant: XILINX INC

Inventor： UIRIAMU ESU KAATAA ,  ROSU EICHI FURIIMAN

IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

Abstract: PURPOSE: To reduce the whole size of a general interconnection structure and an array by providing a special interconnection circuit. CONSTITUTION: A special vertical lead circuit SVC is provided with a special interconnection circuit S1 connected to output leads 1 and programmable access connecting sections P1-P4 and P5-P8 which connect the circuit S1 to desired input leads of morphology adaptive logic arrays (CLEs) 9-1 and 9-3. Similarly, a special horizontal lead circuit SHC is provided with a special interconnection circuit S2 connected to the output lead 2 of the CLE 9-3 and programmable access connecting sections P9-P12 which connect the lead 2 to the desired input lead of a CLE 9-4 and can be programmed to the connecting section of an ordinary connecting structure. Since the circuits S1 and S2 are provided in such a way, the number of ordinary interconnection leads and connecting sections can be reduced from the CLEs and, in addition, the signal speed can be improved through the circuits S1 and S2.