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公开(公告)号：KR1020120108894A
公开(公告)日：2012-10-05
申请号：KR1020110085561
申请日：2011-08-26
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: H03K19/094 , H03K19/20
CPC classification number: H03K19/094 , H03K19/00 , H03K19/02 , H03K19/08 , H03K19/20
Abstract: PURPOSE: An inverter, an NAND gate, and an NOR gate are provided to provide a digital logic gate driven in low consumption power equal to power in a CMOS(Complementary Metal-Oxide Semiconductor) circuit by controlling the flow of a current according to an input and output signal. CONSTITUTION: An inverter comprises a pull-up part(210), a pull down part(220), and a pull up drive part(230). The pull-up part is composed of a second TFT(Thin Film Transistor) outputting a first power supply voltage to an output terminal according to a voltage applied to a gate. The pull down part is composed of a fifth TFT outputting a ground voltage to the output terminal according to the input signal voltage applied to the gate. The pull up drive part applies a second power supply voltage or the ground voltage to the gage in a second TFT according to the input signal.
Abstract translation: 目的：提供一个反相器，一个与非门和一个或非门，以通过控制电流的流动来提供在CMOS（互补金属氧化物半导体）电路中等于功率的低功耗驱动的数字逻辑门 输入和输出信号。 构成：逆变器包括上拉部分（210），下拉部分（220）和上拉驱动部分（230）。 上拉部分由根据施加到栅极的电压将第一电源电压输出到输出端的第二TFT（薄膜晶体管）组成。 下拉部分由根据施加到栅极的输入信号电压向输出端输出接地电压的第五TFT组成。 上拉驱动部件根据输入信号将第二电源电压或接地电压施加到第二TFT中的量规。
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公开(公告)号：KR1020130038722A
公开(公告)日：2013-04-18
申请号：KR1020110103231
申请日：2011-10-10
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
CPC classification number: H02M3/073 , G09G3/3696 , H02M2003/077
Abstract: PURPOSE: A direct current voltage conversion circuit of a liquid crystal display device is provided to correspond to the dispersion of broad threshold voltage by applying positive gate source voltage when turning on a TFT(Thin Film Transistor), and applying negative gate source voltage when turning off the TFT. CONSTITUTION: A main pumping circuit part(710) comprises multiple TFTs(M1-M8). The multiple TFTs are turned on and off by turns. A main pumping circuit part outputs voltage for driving a liquid crystal display device. A switch control signal generating part(720) controls the voltage applied to the gate of multiple thin film transistors with a clock signal inversion.
Abstract translation: 目的：提供液晶显示装置的直流电压转换电路，以便在开启TFT（薄膜晶体管）时施加正栅极源电压，并在转动时施加负栅极源电压，以对应于宽阈值电压的偏差 关掉TFT。 构成：主泵电路部分（710）包括多个TFT（M1-M8）。 多个TFT轮流打开和关闭。 主泵电路部分输出用于驱动液晶显示装置的电压。 开关控制信号生成部（720）通过时钟信号反转来控制施加到多个薄膜晶体管的栅极的电压。
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公开(公告)号：KR101775563B1
公开(公告)日：2017-09-07
申请号：KR1020110085561
申请日：2011-08-26
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: H03K19/094 , H03K19/20
Abstract: 본발명은인버터, NAND 게이트및 NOR 게이트에관한것으로서, 게이트에인가되는전압에따라제1 전원전압을출력단자로출력하는제2 박막트랜지스터로이루어지는풀업부; 게이트에인가되는입력신호에따라그라운드전압을출력단자로출력하는제5 박막트랜지스터로이루어지는풀다운부; 및상기입력신호에따라제2 전원전압또는상기그라운드전압을상기제2 박막트랜지스터의게이트에인가하는풀업구동부를포함한다.
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公开(公告)号：KR1020150131455A
公开(公告)日：2015-11-25
申请号：KR1020140057900
申请日：2014-05-14
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: G09G3/20
Abstract: 게이트구동회로는, 임의의세 개의연속된스테이지들을포함하는복수의스테이지들중, 제1 스테이지의타이밍신호입력단자와제3 스테이지의타이밍신호출력단자가연결되며, 제2 스테이지의캐리단자와제3 스테이지의입력단자가연결된게이트구동회로에있어서, 제2 스테이지는제1 스테이지로부터캐리신호를수신하는입력부, 캐리신호의레벨에따라제1 전압레벨의클럭신호를제1 노드에인가하며, 제2 노드의전압을제1 전압레벨보다상승시키는부트스트래핑부, 제1 노드와 제1 접지단자에연결되며, 제1 노드의전압레벨에따라출력단자의출력신호를제1 접지전압으로풀-다운시키는제1 풀-다운부, 및제1 노드와연결되며, 캐리단자및 타이밍신호출력단자의출력신호를제1 혹은제2 접지전압으로풀-다운시키는제2 풀-다운부를포함하되, 제2 풀-다운부는타이밍신호출력단자에다이오드-커넥션으로연결된제1 트랜지스터및 캐리단자와제1 접지단자에연결된제2 트랜지스터를포함하고, 제1 노드가제2 전압레벨일 때, 제2 트랜지스터가턴-오프상태이면, 캐리단자및 타이밍신호출력단자는제2 접지전압으로풀-다운되고, 제2 트랜지스터가턴-온상태이면, 타이밍신호출력단자는제1 접지전압으로풀-다운되고, 제3 스테이지의제2 노드로부터캐리단자에인가되는방전전압을제1 접지단자로인가하며, 제1 트랜지스터는방전전압이출력단자에인가되지않도록한다. 따라서, 게이트구동회로는출력신호에서리플(Ripple) 현상을감소시킴으로써, 출력신호의효율을향상시킬수 있다. 또한본 발명의실시예에따르면, 이전스테이지에서출력된캐리신호가다음스테이지의입력단자에효과적으로전달될수 있다.
Abstract translation: 门驱动电路技术领域本发明涉及栅极驱动电路。 第一级的定时信号输入端连接到第三级的定时信号输出端。 第二级的进位端连接到第三级的输入端。 第二级包括：输入单元，其从第一级接收进位信号;自举单元，其根据进位信号的电平将第一电压电平的时钟信号施加到第一节点;第一下拉单元 其连接到第一节点和第一接地终端，以及第二下拉单元，其连接到第一节点。 根据本发明的实施例的栅极驱动电路通过减少输出信号中的纹波现象来提高输出信号的效率。
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公开(公告)号：KR1020130129124A
公开(公告)日：2013-11-27
申请号：KR1020130054770
申请日：2013-05-15
Applicant: 건국대학교 산학협력단
IPC: G09G3/20 , H01L29/786
CPC classification number: G09G3/20 , H01L27/1225
Abstract: The present invention relates to a gate driver based on oxide thin-film transistors and comprises: an input part including an input transistor to which a carry signal (CR) of the previous stage is applied; a pull-up part including a pull-up transistor which receives a first clock signal (CLKo) and generates an output signal; a dual pull-down part including a first pull-down transistor and a second pull-down transistor which are alternately turned on and off and connect an output node to a first ground voltage (VSS); a pull-down control part controlling the first and second pull-down transistors so that the transistors are not turned on when the output node is pulled up; and a carry control part stabilizing the output of the next stage by periodically lowering an output carry voltage when the output node is maintained at the first ground voltage.
Abstract translation: 本发明涉及一种基于氧化物薄膜晶体管的栅极驱动器，包括：输入部分，包括施加前一级的进位信号（CR）的输入晶体管; 上拉部分，包括接收第一时钟信号（CLKo）并产生输出信号的上拉晶体管; 包括交替地导通和关断并将输出节点连接到第一接地电压（VSS）的第一下拉晶体管和第二下拉晶体管的双下拉部分; 控制第一和第二下拉晶体管的下拉控制部分，使得当输出节点被上拉时晶体管不导通; 以及进位控制部分，当输出节点保持在第一接地电压时，通过周期性地降低输出进位电压来稳定下一级的输出。
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Patent Agency Ranking
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公开(公告)号：KR101818673B1
公开(公告)日：2018-01-17
申请号：KR1020110103231
申请日：2011-10-10
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
CPC classification number: H02M3/073 , G09G3/3696 , H02M2003/077
Abstract: 본발명은액정표시장치의직류전압변환회로에관한것으로서, 복수의박막트랜지스터를포함하고, 상기복수의박막트랜지스터가교대로온오프되어액정표시장치를구동하기위한전압을출력하는주 펌핑회로부; 및클럭신호반전에의해상기복수의박막트랜지스터의게이트에인가되는전압을제어하는스위치제어신호발생부를포함하되, 각각의박막트랜지스터는양의게이트-소스전압이인가되어온되고, 음의게이트-소스전압이인가되어오프되는것을특징으로한다.
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公开(公告)号：KR1020150069317A
公开(公告)日：2015-06-23
申请号：KR1020130155593
申请日：2013-12-13
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
IPC: G09G3/20
Abstract: 본발명의실시예에따른게이트드라이버회로는복수의스테이지들을포함하고, 각각의스테이지는다이오드커넥션을이루는두 개의입력트랜지스터로구성된입력부, 풀-업트랜지스터와부트스트랩커패시터로구성된풀-업부, 각각두 개의트랜지스터로구성된제 1 및제 2 풀-다운부를포함한다. 실시예에따라서, 입력부및 풀-업부사이의노드에연결된입력커패시터를더 포함할수 있다. 그리고, 출력단자에연결되어하이상태나로우상태의출력신호를다음스테이지로전송하도록구성된캐리부를더 포함할수 있다. 본발명에의하면, 공핍모드특성을갖는산화물박막트랜지스터를안정적으로동작시킬수 있고, 소비전력도감소시킬수 있다. 또한, 게이트드라이버회로의각 스테이지의출력파형이이전스테이지의출력파형과절반씩중첩되게출력함으로써픽셀의충전시간을늘릴수 있다.
Abstract translation: 根据本发明实施例的栅极驱动器电路包括多个级。 每个级包括输入部分，其包括二极管连接的两个输入晶体管，由上拉晶体管和自举电容器组成的上拉部分，以及由两个晶体管组成的下拉部分。 根据实施例，本发明还包括连接到输入部分和上拉部分之间的节点的输入电容器。 本发明还包括一个进位部分，连接到一个输出端，并将一个高或低状态的输出信号传送到下一级。 根据本发明，可以稳定地操作具有耗尽特性的氧化物薄膜晶体管。 功耗可以降低。 此外，栅极驱动电路的各级的输出波形与前一级的输出波形重叠，然后被输出。 由此，可以延长像素的充电时间。
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公开(公告)号：KR1020140029111A
公开(公告)日：2014-03-10
申请号：KR1020130009285
申请日：2013-01-28
Applicant: 한국전자통신연구원 , 건국대학교 산학협력단
Abstract: A single-input type level shifter according to an embodiment of the present invention comprises: an input unit which authorizes a voltage power to a first node in response to an input signal and applies the input signal to a second node in response to a reference signal; a boot strapping unit which authorizes the voltage power to the second node according to different levels of the first node; an output unit which authorizes the input signal to an output terminal in response to the reference signal so that it can apply the voltage power to the output terminal according to the different voltage levels of the first node; and the boot strapping unit includes a capacitor which is located in between the first and the second node. The boot strapping unit increases the voltage level of the first node higher than that of the voltage power once the input signal is converted from a first voltage level into a second voltage level.
Abstract translation: 根据本发明的实施例的单输入型电平移位器包括：输入单元，其响应于输入信号授权对第一节点的电压功率，并响应于参考信号将输入信号施加到第二节点 ; 启动捆扎单元，其根据所述第一节点的不同级别授权所述第二节点的电压功率; 输出单元，其响应于参考信号向输出端授权输入信号，使得其可以根据第一节点的不同电压电平向输出端施加电压功率; 并且所述引导带捆绑单元包括位于所述第一和第二节点之间的电容器。 一旦输入信号从第一电压电平转换为第二电压电平，启动带捆绑单元就增加第一节点的电压高于电压功率的电压电平。
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