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公开(公告)号：KR1020160019595A
公开(公告)日：2016-02-22
申请号：KR1020140103774
申请日：2014-08-11
Applicant: 고려대학교 산학협력단 , 삼성전자주식회사
CPC classification number: G11C11/419 , G11C7/12 , G11C11/412 , G11C2207/002
Abstract: 본발명에따른스태틱랜덤액세스메모리장치는, 단일비트라인구조의메모리셀들을포함하는제 1 메모리셀 어레이, 단일비트라인구조의메모리셀들을포함하는제 2 메모리셀 어레이, 상기제 1 메모리셀 어레이또는상기제 2 메모리셀 어레이중 어레이선택신호에따라선택된메모리셀 어레이의비트라인전압을센싱전압으로출력하고, 비선택된메모리셀 어레이의비트라인전압을기준전압으로출력하는기준전압생성부, 그리고상기센싱전압과상기기준전압의차이를증폭하여출력하는차동센스앰프를포함하되, 상기센싱전압과상기기준전압의로직상태는서로상보이다.
Abstract translation: 根据本发明，静态随机存取存储器件包括：包括单位线结构的存储单元的第一存储单元阵列; 包括单位线结构的存储单元的第二存储单元阵列; 参考电压产生单元，其输出根据阵列选择信号选择的第一和第二存储单元阵列之一的位线电压作为感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压 ; 以及差分读出放大器，其放大并输出感测电压和参考电压之间的差。 感测电压和参考电压的逻辑状态彼此互补。
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公开(公告)号：KR1020080017973A
公开(公告)日：2008-02-27
申请号：KR1020060079933
申请日：2006-08-23
Applicant: 삼성전자주식회사 , 고려대학교 산학협력단
IPC: H03K19/0175 , H04L25/02
CPC classification number: H03K19/018528
Abstract: A data transmitter and a method thereof are provided to adjust a pre-AMP level by using not a current but a signal since a high frequency component of transmitted data increases or decreases according to a channel state. A data transmitter(100) includes a main line driver block(10), a preamplifier unit(20), and a preamplifier controller(30). The main line driver block transmits an input signal to a receiving unit through a transmission path. The preamplifier unit emphasizes a voltage level of the transmitted input signal. The preamplifier controller controls the preamplifier unit. The preamplifier controller adjusts a pre-AMP level of the preamplifier unit to increase a current quantity supplied to the transmission path during transition of the input signal according to a transmission state of the transmission path.
Abstract translation: 提供了一种数据发送器及其方法，用于根据信道状态增加或减少传输数据的高频分量，而不使用电流而不使用信号来调整前置AMP电平。 数据发送器（100）包括主线驱动器块（10），前置放大器单元（20）和前置放大器控制器（30）。 主线驱动器块通过传输路径将输入信号发送到接收单元。 前置放大器单元强调发射的输入信号的电压电平。 前置放大器控制器控制前置放大器单元。 前置放大器控制器根据传输路径的传输状态，调整前置放大器单元的前置放大器电平，以增加在输入信号转换期间提供给传输路径的电流量。
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公开(公告)号：KR102172869B1
公开(公告)日：2020-11-03
申请号：KR20140103774
申请日：2014-08-11
Applicant: 고려대학교 산학협력단 , 삼성전자주식회사
Abstract: 본발명에따른스태틱랜덤액세스메모리장치는, 단일비트라인구조의메모리셀들을포함하는제 1 메모리셀 어레이, 단일비트라인구조의메모리셀들을포함하는제 2 메모리셀 어레이, 상기제 1 메모리셀 어레이또는상기제 2 메모리셀 어레이중 어레이선택신호에따라선택된메모리셀 어레이의비트라인전압을센싱전압으로출력하고, 비선택된메모리셀 어레이의비트라인전압을기준전압으로출력하는기준전압생성부, 그리고상기센싱전압과상기기준전압의차이를증폭하여출력하는차동센스앰프를포함하되, 상기센싱전압과상기기준전압의로직상태는서로상보이다.
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公开(公告)号：KR101297413B1
公开(公告)日：2013-08-19
申请号：KR1020120018814
申请日：2012-02-24
Applicant: 고려대학교 산학협력단
CPC classification number: H03L7/0802 , G06F1/10 , H03K5/00006
Abstract: PURPOSE: An adaptive clock generating apparatus and a method thereof are provided to minimize energy consumption while preventing a clock synchronization error of a circuit. CONSTITUTION: An adaptive clock generating apparatus (10) comprises a fixed frequency divider (100), a replica (200), a counter (300), and a variable frequency divider (500). The fixed frequency divider receives a reference clock, and outputs a clock signal having a period corresponding to an integer multiple of the period of the reference clock. The replica receives the clock signal outputted by the fixed frequency divider, and outputs a clock signal that is delayed as long as a critical path delay of a synchronous circuit. The counter receives an enable signal or a reset signal, which are generated based on the signals outputted by the fixed frequency divider and the replica, further receives the reference clock as its clock signal, and counts the number of cycles of the reference clock while the counter is enabled. The variable frequency divider, based on the number of cycles of the reference clock, generates a clock signal having a period corresponding to an integer multiple of the number of cycles of the reference clock. [Reference numerals] (1) Reference clock; (100) Fixed frequency divider; (2) Divided clock; (200) Replica; (3) Delayed clock; (300) Counter; (4) Counter activation signal; (400) Register; (5) Counter output; (500) Variable frequency divider; (6) Register output; (7) Adaptive output; (AA) Counter reset signal; (BB) Detection unit; (CC) Calculation unit; (DD) Clock generation unit
Abstract translation: 目的：提供自适应时钟发生装置及其方法以最小化能量消耗，同时防止电路的时钟同步误差。 构成：自适应时钟发生装置（10）包括固定分频器（100），副本（200），计数器（300）和可变分频器（500）。 固定分频器接收参考时钟，并输出具有与基准时钟的周期的整数倍相对应的周期的时钟信号。 副本接收由固定分频器输出的时钟信号，并且输出与同步电路的关键路径延迟一样延迟的时钟信号。 计数器接收根据固定分频器和副本输出的信号生成的使能信号或复位信号，进一步接收参考时钟作为其时钟信号，并对参考时钟的周期数进行计数，同时 计数器已启用。 可变分频器基于参考时钟的周期数生成具有对应于参考时钟的周期数的整数倍的周期的时钟信号。 （附图标记）（1）参考时钟; （100）固定分频器; （2）分时钟; （200）副本; （3）延时钟; （300）柜台; （4）计数器激活信号; （400）注册; （5）计数器输出; （500）可变分频器; （6）寄存器输出; （7）自适应输出; （AA）计数器复位信号; （BB）检测单元; （CC）计算单位; （DD）时钟发生单元
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