公开(公告)号：KR1020110077852A

公开(公告)日：2011-07-07

申请号：KR1020090134521

申请日：2009-12-30

Applicant: 고려대학교 산학협력단

Inventor： 노예철 ,  박장현 ,  최성훈 ,  김창선 ,  이석재 ,  박종선

IPC: H03H17/00

Abstract: PURPOSE: A finite impulse response filter is provided to reduce power consumption while suppressing the distortion in the output of a filter by stopping multipliers when input data and a filter coefficient are lower than a certain threshold value. CONSTITUTION: In a finite impulse response filter, a plurality of delay units(110~11n) are serially connected in order to delay input data. A plurality of multipliers(120~12n) multiply the filter coefficient corresponding to the output signal of the plural delays respectively. An adder(130~13n) increases the output signals of a plurality of multipliers. A multiplication blocking activity signal generator(140) stops the operation the plural multiplier in response to a multiplication blocking activation signals. A control signal determination circuit(141) includes a amplitude sensor(142), a control signal generator(143), and delays.

Abstract translation: 目的：提供有限脉冲响应滤波器以减少功耗，同时通过在输入数据和滤波器系数低于某个阈值时停止乘法器来抑制滤波器的输出失真。 构成：在有限脉冲响应滤波器中，多个延迟单元（110〜11n）串联连接以延迟输入数据。 多个乘法器（120〜12n）分别与多个延迟的输出信号对应的滤波器系数相乘。 加法器（130〜13n）增加多个乘法器的输出信号。 乘法阻塞活动信号发生器（140）响应于乘法阻塞激活信号停止多个乘法器的操作。 控制信号确定电路（141）包括振幅传感器（142），控制信号发生器（143）和延迟。