公开(公告)号：KR101396884B1

公开(公告)日：2014-05-19

申请号：KR1020120139792

申请日：2012-12-04

Applicant: 국방과학연구소

Inventor： 노봉수 ,  김수일 ,  박재돈 ,  황호영 ,  이혁준 ,  정인건 ,  정인성 ,  박성주

IPC: H04B7/02 ,  H04L27/26

CPC classification number: H04B7/026 ,  H04L45/125 ,  H04L47/70

Abstract: The present specification relates to a system for allocating a joint bandwidth and selecting a path in an uplink of an IEEE 802.16j based network using a cooperative relaying scheme and a method thereof. For this, the method for allocating the joint bandwidth and selecting the path in the uplink of the IEEE 802.16j based network, which is interworked with mobile terminals, relays and arbitrary base stations included in a plurality of transceiving modes, comprises the steps of: receiving channel information measured by and transmitted from each of the transceiving nodes via the base stations; determining a modulation and coding scheme level (MCS) of each link based on the received channel information via the base stations; and determining the number of symbols on the link used by each of the transceiving nodes according to a joint bandwidth allocation and path selection scheme in the uplink based on the determined MCS level and the average data transmission rate requested by each of the transceiving nodes via the base station.

Abstract translation: 本说明书涉及用于使用协作中继方案及其方法在IEEE 802.16j的网络的上行链路中分配联合带宽和选择路径的系统。 为此，在多个收发模式中包含的与移动终端，中继和任意基站互通的基于IEEE 802.16j的网络的上行链路中分配联合带宽和选择路径的方法包括以下步骤： 接收经由基站从每个收发节点测量和发送的信道信息; 基于经由所述基站的所接收的信道信息，确定每个链路的调制和编码方案级别（MCS）; 以及基于所确定的MCS级别和每个收发节点通过所述收发节点请求的平均数据传输速率，根据所述上行链路中的联合带宽分配和路径选择方案来确定每个收发节点使用的链路上的符号数量 基站。

公开(公告)号：KR100496653B1

公开(公告)日：2005-06-22

申请号：KR1020030031268

申请日：2003-05-16

Applicant: 국방과학연구소

Inventor： 박성주 ,  오형근 ,  오대식 ,  한기택

IPC: G06F11/22

Abstract: 본 발명은 PCI 버스 제어기 코어 및 TBC(Test Bus Controller) 슬레이브 코어를 단일 코어로 통합하여 PCI 버스 제어기능과 함께 테스트 버스 제어기능을 수행할 수 있는 슬레이브 테스트 버스 제어기능을 갖는 PCI 버스 제어기에 관한 것이다.

公开(公告)号：KR1020040098937A

公开(公告)日：2004-11-26

申请号：KR1020030031268

申请日：2003-05-16

Applicant: 국방과학연구소

Inventor： 박성주 ,  오형근 ,  오대식 ,  한기택

IPC: G06F11/22

Abstract: PURPOSE: A PCI(Peripheral Component Interconnect) bus controller having a slave test bus controlling function is provided to perform the PCI bus control and the test bus control at the same time by integrating the PCI bus controller and an ASP(Address Scan Port). CONSTITUTION: A PCI bus controller block(10) includes a PCI bus controller core(11), a BSC(Boundary Scan Cell)(12), and a TAP(Test Access Port)(13). A back-end logic(200) connected to a single board(100) performs a specified process for general operations and gets to be a test board for the process when the test operation is performed. The PCI bus controller core controls communication between the back-end logic and other board or the processor connected to the PCI bus. A TBC(Test Bus Controller) slave core(20) enables the test by connecting the back-end logic with a TBC master. A board address setting part(300) comprises a dip switch or a jumper enabling the user to optionally select the board.

Abstract translation: 目的：提供具有从测试总线控制功能的PCI（外围组件互连）总线控制器，通过集成PCI总线控制器和ASP（地址扫描端口）来同时执行PCI总线控制和测试总线控制。 构成：PCI总线控制器块（10）包括PCI总线控制器核心（11），BSC（边界扫描单元）（12）和TAP（测试访问端口）（13）。 连接到单板（100）的后端逻辑（200）执行一般操作的指定处理，并且在执行测试操作时成为用于进程的测试板。 PCI总线控制器核心控制后端逻辑与其他板卡或连接到PCI总线的处理器之间的通信。 TBC（测试总线控制器）从核心（20）通过将后端逻辑与TBC主机连接起来进行测试。 板地址设置部分（300）包括一个DIP开关或跳线，使用户可以选择选择该板。