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公开(公告)号：KR1020160090541A
公开(公告)日：2016-08-01
申请号：KR1020150010455
申请日：2015-01-22
Applicant: 삼성전기주식회사
IPC: H01L29/66 , H01L29/739
CPC classification number: H01L29/66325 , H01L29/7393
Abstract: 본개시의일 실시형태의전력반도체소자의제조방법은제1 도전형의베이스기판을마련하는단계; 상기베이스기판상에개구부를갖는필드절연영역을형성하는단계; 상기개구부에의해노출된상기베이스기판의상부에상기필드절연영역을덮도록표면반도체층을형성하는단계; 및상기표면반도체층의표면으로부터상기필드절연영역의내부에이르도록트렌치를형성하는단계;를포함할수 있다. 상기필드절연영역이형성됨으로써, 홀캐리어의이동을제한할수 있으며, 소자의전류밀도및 신뢰성을향상시킬수 있다.
Abstract translation: 根据本公开的实施例，功率半导体器件的制造方法包括：制备第一导电性基底的步骤; 在基底基板上形成具有开口单元的场绝缘区域的步骤; 在由所述开口暴露的所述基底基板的上侧形成表面半导体层以覆盖所述场绝缘区域的步骤; 以及从表面半导体层的表面形成在绝缘区域内到达的沟槽的步骤。 可以限制孔载体的移动，并且由于形成了场绝缘区域，所以可以提高电流密度和可靠性。
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公开(公告)号：KR1020150142220A
公开(公告)日：2015-12-22
申请号：KR1020140070611
申请日：2014-06-11
Applicant: 삼성전기주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/7397 , H01L29/7813
Abstract: 본발명은전력반도체소자에관한것으로, 보다상세하게는 N 드리프트영역, N드리프트부의상부에배치된게이트, 게이트에접하도록배치된액티브부, 액티브부의내부에배치되고, 게이트에접하도록배치된에미터부, 액티브부와이격되어배치된인액티브부, 인액티브부의내부에배치되는플로팅부및 액티브부와인액티브부사이의홀 패스(hole pass)를방지하도록인액티브를둘러싸도록배치되는더미게이트를포함하는전력반도체소자를제시한다.
Abstract translation: 功率半导体器件技术领域本发明涉及功率半导体器件。 更具体地，本发明提出一种功率半导体器件，其包括N漂移区域，布置在N漂移部分的上部中的栅极，接触栅极的有源部分，布置在有源部分中的发射极部分 栅极，与有源部分分离的非活性部分，布置在不活动部分中的浮动部分和围绕非活性部分的虚拟栅极，以防止活性部分和非活性部分之间的孔通过。
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公开(公告)号：KR1020150076716A
公开(公告)日：2015-07-07
申请号：KR1020130165241
申请日：2013-12-27
Applicant: 삼성전기주식회사
IPC: H01L29/739 , H01L21/331 , H01L29/78
CPC classification number: H01L29/7397 , H01L29/42368
Abstract: 본개시는표면에형성되는게이트절연층과내부에충전되는도전성물질을포함하는복수의트랜치게이트가형성되어있는제1 도전형의드리프트영역; 상기드리프트영역의상부내측에형성되며, 상기트랜치게이트와접하도록형성되는제2 도전형의바디영역; 상기바디영역의상부내측에형성되며, 상기트랜치게이트와접하도록형성되는제1 도전형의에미터영역; 및상기드리프트영역에형성되며, 상기바디영역의하부에형성되고, 상기트랜치게이트의사이에형성되는정공축적영역;을포함하고, 상기트랜치게이트를높이에따라, 상기바디영역과대응되는부분을제1 게이트부, 상기정공축적영역과대응되는부분을제2 게이트부, 상기드리프트영역과대응되는부분을제3 게이트부라고할 때, 상기제2 게이트부의게이트절연층의두께는상기제3 게이트부의게이트절연층의두께와다른전력반도체소자에관한것이다.
Abstract translation: 本公开涉及一种功率半导体器件，其包括：第一导电类型的漂移区域，其包括多个沟槽栅极，所述多个沟槽栅极包括形成在其表面上的栅绝缘层和填充在其内的导电材料; 第二导电类型的体区，形成在漂移区的上侧的内侧并与沟槽栅极接触; 所述第一导电类型的发射极区域形成在所述主体区域的上侧的内侧并与所述沟槽栅极接触; 并且形成在所述漂移区域上的空穴积聚区域形成在所述体区域的下侧，并且形成在所述沟槽栅极之间。 当沟槽栅极被定义为对应于体区的第一栅极部分时，对应于空穴累积区域的第二栅极部分和对应于漂移区域的第三栅极部分根据高度，栅极绝缘层的厚度 第二栅极部分与第三栅极部分的栅极绝缘层的厚度不同。
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公开(公告)号：KR1020150061973A
公开(公告)日：2015-06-05
申请号：KR1020130146405
申请日：2013-11-28
Applicant: 삼성전기주식회사
IPC: H01L29/739 , H01L29/78 , H01L21/331 , H01L21/336
CPC classification number: H01L29/73 , H01L29/0615 , H01L29/0878 , H01L29/7397 , H01L29/7811 , H01L29/7813
Abstract: 본발명은온-동작시에형성되는채널을통해전류가흐르는활성영역; 상기활성영역의주변에형성되는단부영역; 상기활성영역에형성되며, 일방향으로길게형성되는복수의트랜치; 상기활성영역에형성되며, 상기채널의하부에형성되는제1 도전형의정공축적영역; 및상기단부영역에형성되는제1 도전형의전계제한영역;을포함하고, 상기전계제한영역은상기활성영역과상기단부영역의경계에위치하는상기트랜치의적어도일부를덮도록형성되는전력반도체소자에관한것이다.
Abstract translation: 本发明涉及一种功率半导体器件，其包括有源区，其中形成在工作区中的电流流过形成在有源区周围的端部区域，多个沟槽形成在有源区上 并且在一个方向上形成长;形成在有源区上并形成在沟道的下侧的第一导电型空穴积聚区和形成在端部区域上的第一导电型电场限制区 。 电场限制区域覆盖位于有源区域和端部区域之间的边界中的沟槽的至少一部分。
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Patent Agency Ranking
公开(公告)号：KR1020150018267A
公开(公告)日：2015-02-23
申请号：KR1020130094957
申请日：2013-08-09
Applicant: 삼성전기주식회사
IPC: H01L29/78 , H01L21/336 , H01L29/739
CPC classification number: H01L29/063 , H01L29/0611 , H01L29/0634 , H01L29/0649 , H01L29/1095 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/4916 , H01L29/43 , H01L29/66325 , H01L29/7393 , H01L29/772
Abstract: 본 발명은 제1 도전형의 제1 드리프트 층; 상기 드리프트 층의 두께 방향의 상부에 형성되며, 폭 방향으로 제1 도전형의 제1 반도체 영역과 제2 도전형의 제2 반도체 영역이 교번하여 형성되는 제1 내지 n 리써프 층; 상기 제n 리써프 층의 두께 방향의 상부에 형성되는 제1 도전형의 제2 드리프트 층; 상기 제2 드리프트 층에 형성되며, 상기 제2 반도체 영역의 상부에 형성되는 제2 도전형의 웰 영역; 상기 웰 영역의 상부에 형성되는 제1 도전형의 소스 영역;을 포함하고, 상기 제1 내지 n 리써프 층에 형성되는 상기 제2 반도체 영역의 폭 방향으로 가장 긴 부분의 길이를 P이라고 할 때, P
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-1 n (단, n≥2)인 전력 반도체 소자에 관한 것이다.Abstract translation: 本发明涉及一种功率半导体器件，其包括第一导电类型的第一漂移层，形成在漂移层的厚度方向的上侧上的第一至第n复层，并且通过交替地布置 第一导电类型的第一半导体区域和宽度方向上的第二导电类型的第二半导体区域，第一导电类型的第二漂移层形成在第n导电类型的第n导电类型的厚度方向的上侧上 形成在第二漂移层和第二半导体区域的上侧的第二导电类型的阱区，以及形成在阱区的上侧的第一导电类型的源极区域。 当形成在第1〜第n层上的第2半导体区域的宽度方向的最长长度为P时，满足Pn-1
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公开(公告)号：KR1020140077601A
公开(公告)日：2014-06-24
申请号：KR1020120146587
申请日：2012-12-14
Applicant: 삼성전기주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7397 , H01L29/0615 , H01L29/0619 , H01L29/0688 , H01L29/0847 , H01L29/1095 , H01L29/42372 , H01L29/4238 , H01L29/66348
Abstract: The present invention relates to a power semiconductor device. The power semiconductor device includes a contact which is formed on an active region; a trench gate which is extended from the active region to a first end region and is formed alternately with the contact; a first conductivity type well which is formed between the contact part and the trench gate of the active region; a first conductivity type well extension part which is formed on a portion of the first end region and a second end region; and a first conductivity type field limiting ring which is in contact with the well extension part.
Abstract translation: 功率半导体器件技术领域本发明涉及功率半导体器件。 功率半导体器件包括形成在有源区上的触点; 沟槽栅极，其从有源区域延伸到第一端部区域，并且与接触件交替地形成; 形成在有源区的接触部和沟槽栅之间的第一导电型阱; 形成在第一端部区域的一部分上的第一导电型阱延伸部和第二端区; 以及与阱延伸部分接触的第一导电型场限制环。
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公开(公告)号：KR1020140074027A
公开(公告)日：2014-06-17
申请号：KR1020120142172
申请日：2012-12-07
Applicant: 삼성전기주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7397 , H01L29/1095 , H01L29/41741 , H01L29/66348
Abstract: The power semiconductor device according to the present invention includes: a first conductive type semiconductor substrate which has one side and the other side; a second conductive type drift layer which is formed on the one side of the semiconductor substrate; a second conductive type well layer which is formed on the drift layer; a trench which is formed to reach the drift layer by penetrating the well layer in a thickness direction; a first electrode which is formed in the trench; a second electrode area which is selectively formed on the well layer, is formed with the first area which perpendicularly touches the trench and a second area which is perpendicular to the first area by being separated from the trench in parallel, and has a concentration which is higher than the drift layer; a first conductive type second electrode area which is formed to be in contact with the lateral side of a second conductive type second electrode area on the well layer and has a concentration which is higher than the well layer; and a second electrode which is electrically connected with the second conductive type second electrode area and the first conductive type second electrode area by being formed on the well layer.
Abstract translation: 根据本发明的功率半导体器件包括：具有一侧和另一侧的第一导电型半导体衬底; 第二导电型漂移层，其形成在所述半导体衬底的一侧上; 形成在漂移层上的第二导电类型阱层; 形成为通过沿厚度方向穿透阱层而到达漂移层的沟槽; 形成在沟槽中的第一电极; 选择性地形成在阱层上的第二电极区域形成有与沟槽垂直接触的第一区域和与沟槽平行分离的与第一区域垂直的第二区域，其浓度为 高于漂移层; 第一导电类型的第二电极区域，其形成为与阱层上的第二导电类型的第二电极区域的侧面接触并且具有高于阱层的浓度; 以及通过形成在所述阱层上而与所述第二导电型第二电极区域和所述第一导电型第二电极区域电连接的第二电极。
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公开(公告)号：KR1020140073325A
公开(公告)日：2014-06-16
申请号：KR1020120141454
申请日：2012-12-06
Applicant: 삼성전기주식회사
IPC: H01L29/739 , H01L29/78 , H01L21/331
CPC classification number: H01L29/7395 , H01L29/0619 , H01L29/0638 , H01L29/404 , H01L29/423 , H01L29/66333
Abstract: The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device according to one embodiment of the present invention includes a first conductivity type drift layer; a second conductivity type end layer which is formed in the upper part of the drift layer; and a first conductivity type channel stop layer of high concentration which is formed in the end part of the drift layer. According to one embodiment of the present invention, the depth of the channel stop layer is greater than that of the end layer.
Abstract translation: 功率半导体器件及其制造方法技术领域本发明涉及功率半导体器件及其制造方法。 根据本发明的一个实施例的功率半导体器件包括第一导电型漂移层; 第二导电型端层，形成在漂移层的上部; 以及形成在漂移层的端部的高浓度的第一导电型沟道阻挡层。 根据本发明的一个实施例，通道阻挡层的深度大于端层的深度。
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公开(公告)号：KR1020140067445A
公开(公告)日：2014-06-05
申请号：KR1020120134700
申请日：2012-11-26
Applicant: 삼성전기주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/402 , H01L29/0619 , H01L29/41741 , H01L29/66348 , H01L29/7397
Abstract: A power semiconductor device according to an embodiment of the present invention comprises: a second conductive type first junction termination extension (JTE) layer formed to be in contact with one side of a second conductive type well layer; a second conductive type second JTE layer formed on a same line of the second conductive type first JTE layer and to be spaced apart from the second conductive type first JTE layer in the longitudinal direction of a substrate; and a poly silicon layer formed to be in contact with the second conductive type well layer and the second conductive type first JTE layer.
Abstract translation: 根据本发明的实施例的功率半导体器件包括：形成为与第二导电类型阱层的一侧接触的第二导电型第一接合端接延伸（JTE）层; 第二导电类型的第二JTE层，形成在第二导电型第一JTE层的同一线上，并且在基板的纵向方向上与第二导电型第一JTE层间隔开; 以及形成为与第二导电类型阱层和第二导电型第一JTE层接触的多晶硅层。
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