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公开(公告)号：KR1020160044338A
公开(公告)日：2016-04-25
申请号：KR1020140139247
申请日：2014-10-15
Applicant: 삼성전기주식회사
CPC classification number: H01G4/30 , H01G4/012 , H01G4/1227 , H01G4/232
Abstract: 본발명의일 실시예에따른칩 부품은, 복수의제1 및제2 유전체층이교대로배치되는용량형성층을포함하는세라믹본체및 상기세라믹본체의길이방향의양 측면에배치되는외부전극; 을포함하고, 상기용량형성층은, 상기복수의제1 유전체층상에서로이격되어배치되며, 상기세라믹본체의길이방향의양 측면을통해노출되어상기외부전극과연결되는제1 및제2 내부전극및 상기복수의제2 유전체층상에배치되며, 상기제1 및제2 내부전극의일부와중첩되는플로팅(floating) 전극을포함하고, 상기세라믹본체는, 상기세라믹본체의상면및 하면중 적어도일면과상기용량형성층사이에배치되며, 상기세라믹본체의길이방향의양 측면으로노출되는제1 및제2 더미전극이배치되는복수의제3 유전체층을갖는보호층을더 포함하며, 상기보호층은, 상기제1 및제2 더미전극사이에배치되는제3 더미전극을더 포함할수 있다.
Abstract translation: 根据本发明的实施例的芯片部件包括陶瓷体，其包括交替布置多个第一和第二电介质层的电容形成层和布置在陶瓷体的两个纵向侧的外部电极。 电容形成层包括第一内部电极和第二内部电极，该第一内部电极和第二内部电极分别设置在多个第一电介质层上，并且通过暴露于陶瓷体的两个纵向侧面而与外部电极连接， 布置在所述多个第二电介质层上并与所述第一和第二内部电极的一部分重叠。 陶瓷体还包括设置在陶瓷体的上表面和下表面中的至少一个和电容形成层之间的保护层，并且具有多个第三电介质层，其中第一和第二虚拟电极暴露于两个纵向侧 的陶瓷体。 保护层还可以包括布置在第一和第二虚拟电极之间的第三虚拟电极。
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公开(公告)号：KR1020140032179A
公开(公告)日：2014-03-14
申请号：KR1020120098748
申请日：2012-09-06
Applicant: 삼성전기주식회사
Abstract: The present invention relates to multi-layered ceramic capacitor and a manufacturing method thereof. The multi-layered ceramic capacitor according to the present invention includes: a lower laminating part which corresponds to the 1/3 of the thickness of a whole chip and has the multi-layered laminating structure of a first sheet having a predetermined thickness; a central laminating part which is positioned in the upper part of the lower laminating part, corresponds to the 1/3 of the thickness of the whole chip, and has the multi-layered laminating structure of a second sheet which is relatively thicker than the lower laminating part; and an upper laminating part which is positioned in the upper part of the central laminating part, corresponds to the 1/3 of the thickness of the whole chip, and has the multi-layered laminating structure of the first sheet which is same as the lower laminating part, wherein the application rate of the central laminating part is 7-20% of the whole laminating structure. The present invention is able to remarkably reduce the short rate of an electrode by releasing the aggregation phenomenon of an internal electrode which is caused by an overheating because a laminating part is formed by laminating the central part of a chip laminating structure with a sheet which is relatively thicker than the upper and lower parts of the laminating structure. [Reference numerals] (AA) Sheet 2 (heterogeneous sheet)
Abstract translation: 多层陶瓷电容器及其制造方法技术领域本发明涉及多层陶瓷电容器及其制造方法。 根据本发明的多层陶瓷电容器包括：下层叠部分，其对应于整个芯片的厚度的1/3，并具有具有预定厚度的第一片的多层层压结构; 位于下层叠部的上部的中央层叠部相当于整个片的厚度的1/3，具有比下层更厚的第二片的多层层叠结构 层压零件; 并且位于中央层叠部的上部的上层叠部相当于整个片的厚度的1/3，并且具有与下层相同的第一片的多层层叠结构 层压部分，其中中心层压部分的施加率为整个层压结构的7-20％。 本发明能够通过解除由于过热引起的内部电极的聚集现象而显着降低电极的短路速度，因为层压部分是通过将芯片层压结构的中心部分与片材层压结构的中心部分 比层压结构的上部和下部相对较厚。 （附图标记）（AA）片材2（异质片材）
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