公开(公告)号：KR1020100060149A

公开(公告)日：2010-06-07

申请号：KR1020080118615

申请日：2008-11-27

Applicant: 삼성전자주식회사

Inventor： 서재용 ,  강구관 ,  강태훈 ,  박홍식 ,  김중현

IPC: G11C29/04

CPC classification number: H03K19/173 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: An anti fuse circuit of an inverter type in a semiconductor device is provided to secure the reliability in a low voltage by using a transistor as a fuse element. CONSTITUTION: A PMOS-transistor(P1) includes a gate connected to a driving voltage and also includes a source connected to an anti-pad terminal. The PMOS transistor has a source receiving AC and performs a fuse program. The NMOS transistor(N1) is connected to the drain of the PMOS transistor and includes a source connected to the ground. The NMOS transistor receives a program control signal through the gate. A sub STI area is at least two regions.

Abstract translation: 目的：提供半导体器件中的逆变器类型的反熔丝电路，通过使用晶体管作为熔丝元件来确保低电压的可靠性。 构成：PMOS晶体管（P1）包括连接到驱动电压的栅极，并且还包括连接到反焊盘端子的源极。 PMOS晶体管具有源接收AC并执行熔丝程序。 NMOS晶体管（N1）连接到PMOS晶体管的漏极，并且包括连接到地的源极。 NMOS晶体管通过栅极接收编程控制信号。 子STI区域是至少两个区域。

公开(公告)号：KR1020100002357A

公开(公告)日：2010-01-07

申请号：KR1020080062214

申请日：2008-06-30

Applicant: 삼성전자주식회사

Inventor： 서재용 ,  강태훈 ,  강구관 ,  박홍식 ,  배성훈 ,  이민경 ,  이영윤

IPC: G01R31/26 ,  H01L21/66

CPC classification number: G01R31/2601 ,  G01R31/2817 ,  G01R31/2855 ,  H01L21/67271 ,  H01L22/30

Abstract: PURPOSE: A multi burn-in test method is provided to maximize a production yield by balancing the stress applied to a specific defect of a node, thereby preventing the deterioration of a specific circuit. CONSTITUTION: A pre-test executes in order to detect for defects in a semiconductor chip(S100). A burn-in board is installed in a chamber(S200). A burn-in test executes after multi-stress is applied to the pre-tested semiconductor chip(S300). A post-test executes to detect for defects in the burn-in tested semiconductor chip(S400). The burn-in test checks the semiconductor chip and metal wiring. The burn-in board is extracted from a chamber(S500).

Abstract translation: 目的：提供一种多重老化测试方法，通过平衡应用于节点的特定缺陷的应力来最大化产量，从而防止特定电路的劣化。 构成：为了检测半导体芯片中的缺陷，执行预测试（S100）。 老化板安装在室内（S200）。 在将多重应力施加到预先测试的半导体芯片上之后执行老化测试（S300）。 执行后验测试以检测老化测试半导体芯片中的缺陷（S400）。 老化测试检查半导体芯片和金属布线。 从室中取出老化板（S500）。

公开(公告)号：KR1020000039175A

公开(公告)日：2000-07-05

申请号：KR1019980054425

申请日：1998-12-11

Applicant: 삼성전자주식회사

Inventor： 전찬웅 ,  강태훈 ,  강구관 ,  황삼진

IPC: H01L21/76

Abstract: PURPOSE: A semiconductor chip is provided which is to prevent the generated cracks from intruding into the semiconductor chip by forming a trench on the scribe line and in the semiconductor chip. CONSTITUTION: A semiconductor chip is provided wherein many trenches(13) are formed on the scribe line(11), in the semiconductor chip(10), and into the space, except for the portion where the device had been formed, while the shapes of the transaction of the trench(13) are a circle, an ellipse, a triangle, a square, a rectangle, a pentagon, a hexagon, a lozenge, star or iron dumb-bells, and the shapes of vertical section thereof are U-type, V-type or water jar-type.

Abstract translation: 目的：提供半导体芯片，其通过在划线和半导体芯片中形成沟槽来防止产生的裂纹侵入半导体芯片。 构成：提供半导体芯片，其中在半导体芯片（10）中的划线（11）上形成许多沟槽（13），并且除了形成器件的部分之外，还形成了空间 沟槽（13）的交易是圆形，椭圆形，三角形，方形，矩形，五边形，六角形，菱形，星形或铁哑铃，其垂直截面的形状为U 型，V型或水壶型。