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公开(公告)号：KR100832104B1
公开(公告)日：2008-05-27
申请号：KR1020060086353
申请日：2006-09-07
Applicant: 삼성전자주식회사
IPC: H01L21/8242
CPC classification number: H01L27/11507 , H01L21/76849 , H01L21/7687 , H01L23/5226 , H01L27/11502 , H01L28/55 , H01L2924/0002 , H01L2924/00
Abstract: 반도체 메모리 장치 및 그 형성 방법이 제공된다. 상기 형성 방법은 도전영역을 갖는 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막을 식각하여 상기 도전영역을 노출하는 콘택홀을 형성하는 단계; 상기 콘택홀의 측벽 및 저면을 덮는 장벽 금속막과, 상기 장벽 금속막을 개재하여 상기 콘택홀 내에 콘택 플러그를 형성하는 단계; 식각 공정을 수행하여, 상기 장벽 금속막과 상기 콘택 플러그를 리세스시키고, 상기 콘택 플러그 상부면을 상기 장벽 금속막 상부면 위로 돌출시키는 단계; 상기 리세스된 장벽금속막과 상기 리세스된 콘택 플러그를 덮는 캡핑 플러그를 형성하는 단계; 및 상기 캡핑 플러그 상에 커패시터를 형성하는 단계를 포함한다.
강유전체, 콘택 플러그, 캡핑 플러그-
公开(公告)号：KR1020080022772A
公开(公告)日：2008-03-12
申请号：KR1020060086353
申请日：2006-09-07
Applicant: 삼성전자주식회사
IPC: H01L21/8242
CPC classification number: H01L27/11507 , H01L21/76849 , H01L21/7687 , H01L23/5226 , H01L27/11502 , H01L28/55 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device and a fabricating method thereof are provided to prevent metal material of a contact plug from remaining on a sidewall of a contact hole by simultaneously etching the contact plug and a barrier metal layer. Insulating layers(120-150) are formed on a semiconductor substrate(110) having a conductive region. The insulating regions are etched to form a contact hole(151) for exposing the conductive region. A barrier metal layer(153) for covering a sidewall and a bottom of the contact hole is formed, and then a contact plug(155) is formed in the contact hole by interposing the barrier metal layer between the contact plug and the contact hole. An etching process is performed on the substrate to recess the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug(157) is formed to cover the recessed barrier metal layer and the recessed contact plug. A capacitor(170) is formed on the capping plug.
Abstract translation: 提供半导体器件及其制造方法，以通过同时蚀刻接触插塞和阻挡金属层来防止接触插塞的金属材料残留在接触孔的侧壁上。 绝缘层（120-150）形成在具有导电区域的半导体衬底（110）上。 绝缘区域被蚀刻以形成用于暴露导电区域的接触孔（151）。 形成用于覆盖接触孔的侧壁和底部的阻挡金属层（153），然后通过将阻挡金属层插入在接触插塞和接触孔之间而在接触孔中形成接触插塞（155）。 在基板上进行蚀刻处理，以使阻挡金属层和接触塞以使得接触插塞的顶表面向上突出超过阻挡金属层的顶表面的方式进行。 形成封盖塞（157）以覆盖凹陷的阻挡金属层和凹入的接触插塞。 在封盖上形成电容器（170）。
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公开(公告)号：KR1020070081704A
公开(公告)日：2007-08-17
申请号：KR1020060013867
申请日：2006-02-13
Applicant: 삼성전자주식회사
IPC: H01L27/105
CPC classification number: H01L23/5223 , H01L27/10855 , H01L28/55 , H01L28/65
Abstract: A ferroelectric memory device and its manufacturing method are provided to shorten a turnaround time by forming a plate line on an additional top electrode without using a via hole. A bottom interlayer dielectric(200) is formed on a semiconductor substrate(100) Plural capacitors(310) penetrate the bottom interlayer dielectric to be connected to a plug. A top interlayer dielectric(300) is formed to cover the capacitors, and an additional top electrode(410) is commonly connected to the top electrode of the capacitors. An interconnection(430) is formed to cover the additional top electrode to be connected to the additional top electrode, and comes in contact with the top interlayer dielectric.
Abstract translation: 提供铁电存储器件及其制造方法，通过在附加的顶部电极上形成板状线而不使用通孔来缩短周转时间。 底部层间电介质（200）形成在半导体衬底（100）上。多个电容器（310）穿透底部层间电介质以连接到插头。 形成顶层层间电介质（300）以覆盖电容器，另外的顶部电极（410）共同连接到电容器的顶部电极。 形成互连（430）以覆盖要连接到附加顶部电极的附加顶部电极，并与顶部层间电介质接触。
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