公开(公告)号：KR1020140002379A

公开(公告)日：2014-01-08

申请号：KR1020120070998

申请日：2012-06-29

Applicant: 삼성전자주식회사 ,  (주)티아이스퀘어

Inventor： 김재환 ,  이길수 ,  최도연

IPC: H04L29/06 ,  H04L12/16 ,  H04M3/42

CPC classification number: H04M3/5191 ,  H04M3/5166 ,  H04M2203/253

Abstract: The present invention relates to a method and a system for transmitting information between an electronic device and a call center system by using an IP telephony technology. A method for providing a display type automatic response service (ARS) in an ARS system comprises the following steps: the electronic device requests the call center system to make a call connection; a switch device generates a response message including information on connection to a web ARS server with respect to the request and transmits the response message to the electronic device; and the electronic device forms a data session to the web ARS server by using the received information on connection to the web ARS server and provides the display type ARS by using the information received from the web ARS server. [Reference numerals] (100-1,100-2,100-3) Terminal; (110) VoIP service provider; (112) Switch device; (120) Internet call center system; (AA) Terminal connected over wireless/wired internet service provider; (BB) Internet

Abstract translation: 本发明涉及通过使用IP电话技术在电子设备和呼叫中心系统之间传送信息的方法和系统。 一种用于在ARS系统中提供显示型自动应答服务（ARS）的方法包括以下步骤：电子设备请求呼叫中心系统进行呼叫连接; 切换装置生成响应消息，该响应消息包括关于与所述请求相关的关于ARS服务器的连接的信息，并将所述响应消息发送到所述电子设备; 并且电子设备通过使用接收到的与Web ARS服务器连接的信息来形成到ARS服务器的数据会话，并通过使用从web ARS服务器接收的信息来提供显示类型ARS。 （附图标记）（100-1,100-2,100-3）端子; （110）VoIP服务提供商; （112）开关装置; （120）互联网呼叫中心系统; （AA）通过无线/有线互联网服务提供商连接的终端; （BB）互联网

公开(公告)号：KR1020090081681A

公开(公告)日：2009-07-29

申请号：KR1020080007677

申请日：2008-01-24

Applicant: 삼성전자주식회사

Inventor： 최도연 ,  김재현 ,  김송이 ,  김휘산

IPC: H01L27/105

Abstract: A ferroelectric random access memory and a manufacturing method thereof are provided to prevent deterioration of a ferroelectric capacitor due to the hydrogen by including a hydrogen barrier layer. A ferroelectric random access memory device includes a plurality of ferroelectric capacitors(510), an additional top electrode(530), a hydrogen barrier layer(542), and an etch stop layer(550). The plurality of ferroelectric capacitors are formed on a semiconductor substrate(100). The additional top electrode is commonly connected to a top electrode(516) of the plurality of ferroelectric capacitors. The hydrogen barrier layer is formed on the additional top electrode. The etch stop layer is formed on the hydrogen barrier layer.

Abstract translation: 提供铁电随机存取存储器及其制造方法，以通过包括氢阻挡层来防止由于氢而导致的铁电电容器的劣化。 铁电随机存取存储器件包括多个铁电电容器（510），附加顶电极（530），氢势垒层（542）和蚀刻停止层（550）。 多个铁电电容器形成在半导体衬底（100）上。 另外的顶部电极通常连接到多个铁电电容器的顶部电极（516）。 氢阻挡层形成在附加的顶部电极上。 蚀刻停止层形成在氢阻挡层上。

公开(公告)号：KR1020090052720A

公开(公告)日：2009-05-26

申请号：KR1020070119350

申请日：2007-11-21

Applicant: 삼성전자주식회사

Inventor： 정동진 ,  김휘산 ,  홍영기 ,  안우송 ,  정주영 ,  고한경 ,  최도연

IPC: H01L27/105

Abstract: 강유전체 메모리 장치 및 이를 제조하는 방법에서, 하부 전극 위에 절연막이 구비되고, 하부 전극과 오버랩되는 절연막의 일부분에는 곡면으로 정의되는 반구 형상의 콘택홀을 형성된다. 콘택홀을 정의하는 곡면 위에 배리어 도전막, 강유전체막, 및 상부 전극이 순차적으로 적층되고, 그 결과 상부 전극, 배리어 도전막, 강유전체막, 및 상부 전극으로 이루어지는 커패시터가 형성된다. 상부 전극은 콘택홀의 형상에 대응하여 하부 전극 측으로 볼록한 형상을 가져 면적이 증가한다. 따라서, 커패시터의 축전 용량이 증가한다.

公开(公告)号：KR1020100087564A

公开(公告)日：2010-08-05

申请号：KR1020090006655

申请日：2009-01-28

Applicant: 삼성전자주식회사

Inventor： 박명순 ,  안은철 ,  정현수 ,  김석호 ,  최도연 ,  천진호

IPC: H01L21/60

CPC classification number: H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: PURPOSE: A method for forming a connection terminal including a solder unit and a solder unit supporter is provided to efficiently reduce an external impact by changing the propagation direction of a crack. CONSTITUTION: A substrate with a UBM(Under Bump Metallurgy)(116) is prepared. A solder unit(141) comprised of a lower side of a cylindrical shape and an upper side of a sphere shape is formed. The lower side is combined with the UBM. A solder unit supporter(130) is formed on the substrate and surrounds the lower side. The solder unit supporter is arranged on the UBM.

Abstract translation: 目的：提供一种用于形成包括焊料单元和焊料单元支撑件的连接端子的方法，以通过改变裂纹的传播方向来有效地减少外部冲击。 构成：制备了具有UBM（Under Bump Metallurgy）（116）的底物。 形成由圆柱形的下侧和球形的上侧构成的焊接单元（141）。 下侧与UBM组合。 焊料单元支撑件（130）形成在基板上并且围绕下侧。 焊接单元支架安装在UBM上。

公开(公告)号：KR1020090081070A

公开(公告)日：2009-07-28

申请号：KR1020080006935

申请日：2008-01-23

Applicant: 삼성전자주식회사

Inventor： 정주영 ,  최도연 ,  홍영기 ,  고한경

IPC: H01L27/105

Abstract: A ferroelectric random access memory and a manufacturing method thereof for improving the adhesion of ferroelectric and upper electrode are provided to prevent the defect of the interfacial property. A ferroelectric random access memory comprises a first interlayer insulating film(128), a contact(132) for a bottom electrode, a ferroelectric pattern(134), a second inter metal dielectric(138), and a first reaction-preventing film pattern. The first interlayer insulating film is equipped on the substrate. The contact for the bottom electrode is equipped within the first interlayer insulating film. The ferroelectric pattern contacts the contact for the bottom electrode. The second inter metal dielectric comprises the contact hole exposing one part of the ferroelectric pattern. The first reaction-preventing film pattern is equipped in the upper side of the second inter metal dielectric. The second reaction-preventing film pattern is equipped in the side wall of the contact hole.

Abstract translation: 提供了一种用于改善铁电体和上电极的粘附性的铁电随机存取存储器及其制造方法，以防止界面特性的缺陷。 铁电随机存取存储器包括第一层间绝缘膜（128），用于底部电极的触点（132），铁电图案（134），第二金属间介电层（138）和第一反应防止膜图案。 第一层间绝缘膜设置在基板上。 第一层间绝缘膜内装有用于底部电极的接触。 铁电图案接触底部电极的触点。 第二金属间电介质包括暴露一部分铁电图案的接触孔。 第一反应防止膜图案配置在第二金属间介电体的上侧。 第二反应防止膜图案装配在接触孔的侧壁中。

公开(公告)号：KR1020090013387A

公开(公告)日：2009-02-05

申请号：KR1020070077457

申请日：2007-08-01

Applicant: 삼성전자주식회사

Inventor： 김재현 ,  양민호 ,  백현석 ,  박정훈 ,  최도연

IPC: H01L27/108 ,  H01L27/105

CPC classification number: H01L28/57 ,  H01L23/3171 ,  H01L27/0805 ,  H01L27/11502

Abstract: A ferroelectric memory device and manufacturing method thereof are provided to prevent the hydrogen(H) from penetrating into the capacitor and to prevent the characteristic deterioration of capacitor. The method of manufacturing the ferroelectric memory device comprises as follows. The ferroelectric film(220) is formed on the bottom electrode(210). The upper electrode(230) is formed on the ferroelectric film. The insulating layer(400) is formed to cover the capacitor(200). The insulating layer is partially eliminated to expose the upper electrode. The protective film for covers the insulating layer the exposed upper electrode is formed to prevent the hydrogen penetration. The assisted electrode layer including the first metal on the protective film is formed.

Abstract translation: 提供一种铁电存储器件及其制造方法，以防止氢（H）渗入电容器并防止电容器的特性劣化。 铁电存储器件的制造方法如下。 铁电体膜（220）形成在底部电极（210）上。 上电极（230）形成在铁电体膜上。 绝缘层（400）形成为覆盖电容器（200）。 绝缘层被部分地消除以暴露上电极。 用于覆盖绝缘层的保护膜形成暴露的上电极以防止氢穿透。 在保护膜上形成包含第一金属的辅助电极层。

公开(公告)号：KR100755373B1

公开(公告)日：2007-09-04

申请号：KR1020060089496

申请日：2006-09-15

Applicant: 삼성전자주식회사

Inventor： 최도연 ,  김휘산 ,  주흥진

IPC: H01L21/28 ,  H01L27/108

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/57

Abstract: A contact structure having a conductive oxide layer, a ferroelectric memory device employing the same, and manufacturing methods thereof are provided to prevent the generation of a minute crack between a contact plug and a lower electrode by using a conductive protection pattern made of the conductive oxide layer. An interlayer dielectric(131) is provided on a semiconductor substrate. A contact plug(141) passes through the interlayer dielectric and is comprised of a metal plug(135) and a buffer plug(140) which are sequentially laminated. A conductive protection pattern(145a) is formed with a conductive oxide layer and covers the contact plug. A lower electrode(156a), a ferroelectric pattern(157a), and an upper electrode(159a) are sequentially laminated on the conductive protection pattern. An insulating protective layer(165) covers the lower electrode, the ferroelectric pattern, and the upper electrode. The metal plug is made of tungsten. The buffer plug is made of metal nitride or conductive oxide.

Abstract translation: 提供具有导电氧化物层的接触结构，使用该导电氧化物层的铁电存储器件及其制造方法，以通过使用由导电氧化物制成的导电保护图案来防止接触插塞和下部电极之间的微小裂纹的产生 层。 在半导体衬底上设置层间电介质（131）。 接触塞141穿过层间电介质，并由依次层压的金属插塞135和缓冲塞140构成。 导电保护图案（145a）形成有导电氧化物层并且覆盖接触插塞。 下电极（156a），铁电体图案（157a）和上电极（159a）依次层叠在导电保护图案上。 绝缘保护层（165）覆盖下电极，铁电体图案和上电极。 金属插头由钨制成。 缓冲塞由金属氮化物或导电氧化物制成。

公开(公告)号：KR1020070063748A

公开(公告)日：2007-06-20

申请号：KR1020050123902

申请日：2005-12-15

Applicant: 삼성전자주식회사

Inventor： 박명순 ,  정현수 ,  이인영 ,  최도연

IPC: H01L23/12 ,  H01L23/52

CPC classification number: H01L25/073 ,  H01L21/76 ,  H01L23/481 ,  H01L24/26

Abstract: A wafer level package and its manufacturing method are provided to improve the reliability of an electric connection between wafer level packages by inputting an electric signal to a semiconductor chip or drawing the electric signal from the semiconductor chip using at least two paths. A conductive pattern(130) is prolonged along an upper surface of a semiconductor chip(110). The conductive pattern is electrically connected with the chip. An insulating photoresist structure(120) is formed on the chip and the conductive pattern. The insulating photoresist structure has a contact hole for exposing partially the conductive pattern to the outside. A conductive member(140) is filled in the contact hole to be electrically connected to the conductive pattern. A penetration electrode(132) is prolonged to a lower surface of the chip through the chip from the conductive pattern. An anisotropic conductive adhesive layer(150) is formed on the lower surface of the chip to allow the flow of an electric signal to the penetration electrode. A conductive layer is formed under the anisotropic conductive adhesive layer in order to be electrically connected with the penetration electrode via the anisotropic conductive adhesive layer.

Abstract translation: 提供了晶片级封装及其制造方法，以通过使用至少两条路径将电信号输入到半导体芯片或从半导体芯片绘制电信号来提高晶片级封装之间的电连接的可靠性。 导电图案（130）沿着半导体芯片（110）的上表面延长。 导电图案与芯片电连接。 在芯片和导电图案上形成绝缘光致抗蚀剂结构（120）。 绝缘光致抗蚀剂结构具有用于将导电图案部分地暴露于外部的接触孔。 导电构件（140）填充在接触孔中以与导电图案电连接。 穿透电极（132）通过芯片从导电图案延伸到芯片的下表面。 在芯片的下表面上形成各向异性导电粘合剂层（150），以允许电信号流向穿透电极。 在各向异性导电粘合剂层之下形成导电层，以便通过各向异性导电粘合剂层与穿透电极电连接。

公开(公告)号：KR100832104B1

公开(公告)日：2008-05-27

申请号：KR1020060086353

申请日：2006-09-07

Applicant: 삼성전자주식회사

Inventor： 정주영 ,  주석호 ,  박정훈 ,  주흥진 ,  김휘산 ,  강승국 ,  최도연

IPC: H01L21/8242

CPC classification number: H01L27/11507 ,  H01L21/76849 ,  H01L21/7687 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체 메모리 장치 및 그 형성 방법이 제공된다. 상기 형성 방법은 도전영역을 갖는 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막을 식각하여 상기 도전영역을 노출하는 콘택홀을 형성하는 단계; 상기 콘택홀의 측벽 및 저면을 덮는 장벽 금속막과, 상기 장벽 금속막을 개재하여 상기 콘택홀 내에 콘택 플러그를 형성하는 단계; 식각 공정을 수행하여, 상기 장벽 금속막과 상기 콘택 플러그를 리세스시키고, 상기 콘택 플러그 상부면을 상기 장벽 금속막 상부면 위로 돌출시키는 단계; 상기 리세스된 장벽금속막과 상기 리세스된 콘택 플러그를 덮는 캡핑 플러그를 형성하는 단계; 및 상기 캡핑 플러그 상에 커패시터를 형성하는 단계를 포함한다.
강유전체, 콘택 플러그, 캡핑 플러그

公开(公告)号：KR1020080022772A

公开(公告)日：2008-03-12

申请号：KR1020060086353

申请日：2006-09-07

Applicant: 삼성전자주식회사

Inventor： 정주영 ,  주석호 ,  박정훈 ,  주흥진 ,  김휘산 ,  강승국 ,  최도연

IPC: H01L21/8242

CPC classification number: H01L27/11507 ,  H01L21/76849 ,  H01L21/7687 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a fabricating method thereof are provided to prevent metal material of a contact plug from remaining on a sidewall of a contact hole by simultaneously etching the contact plug and a barrier metal layer. Insulating layers(120-150) are formed on a semiconductor substrate(110) having a conductive region. The insulating regions are etched to form a contact hole(151) for exposing the conductive region. A barrier metal layer(153) for covering a sidewall and a bottom of the contact hole is formed, and then a contact plug(155) is formed in the contact hole by interposing the barrier metal layer between the contact plug and the contact hole. An etching process is performed on the substrate to recess the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug(157) is formed to cover the recessed barrier metal layer and the recessed contact plug. A capacitor(170) is formed on the capping plug.

Abstract translation: 提供半导体器件及其制造方法，以通过同时蚀刻接触插塞和阻挡金属层来防止接触插塞的金属材料残留在接触孔的侧壁上。 绝缘层（120-150）形成在具有导电区域的半导体衬底（110）上。 绝缘区域被蚀刻以形成用于暴露导电区域的接触孔（151）。 形成用于覆盖接触孔的侧壁和底部的阻挡金属层（153），然后通过将阻挡金属层插入在接触插塞和接触孔之间而在接触孔中形成接触插塞（155）。 在基板上进行蚀刻处理，以使阻挡金属层和接触塞以使得接触插塞的顶表面向上突出超过阻挡金属层的顶表面的方式进行。 形成封盖塞（157）以覆盖凹陷的阻挡金属层和凹入的接触插塞。 在封盖上形成电容器（170）。