公开(公告)号：KR100452328B1

公开(公告)日：2004-10-12

申请号：KR1020020045287

申请日：2002-07-31

Applicant: 삼성전자주식회사

Inventor： 강창만 ,  김정열

IPC: G11C11/40

CPC classification number: G11C7/1066 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072

Abstract: A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.

Abstract translation: 数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。 多个寄存器输出选择开关对由相应的公共有源区连接。 第一数据组选择开关连接到第一组多个寄存器输出选择开关的公共有源区。 第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有源区。 输出驱动器连接到第一和第二数据组选择开关。

公开(公告)号：KR100434510B1

公开(公告)日：2004-06-05

申请号：KR1020020047380

申请日：2002-08-10

Applicant: 삼성전자주식회사

Inventor： 강창만

IPC: G11C7/12

CPC classification number: G11C7/1048 ,  G11C7/1006

Abstract: An integrated circuit device includes first and second complementary data line pairs, e.g., global or local I/O data line pairs, disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween. An equalization transistor includes respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair. A first precharge transistor includes the first source/drain region, a third source/drain region in the substrate displaced from the first source/drain region along the first direction, and a first precharge transistor gate electrode disposed on the substrate between the first and third source/drain regions. A second precharge transistor includes the second source/drain region, a fourth source/drain region in the substrate displaced from the second source/drain region along the first direction, and a second precharge transistor gate electrode disposed on the substrate between the second and fourth source/drain regions. A precharge voltage bus conductor is disposed on the substrate and is electrically coupled to the third and fourth source/drain regions.

Abstract translation: 集成电路器件包括设置在衬底上并沿着第一方向延伸的第一和第二互补数据线对，例如全局或局部I / O数据线对，第一和第二互补数据线对被布置为使得第一和第二 第一互补数据线对的数据线具有设置在其间的第二互补数据线对的第一数据线。 均衡晶体管包括衬底中的相应的第一和第二源极/漏极区域，其分别耦合到第一互补数据线对的第一和第二数据线中的相应的一个;以及均衡晶体管栅电极，设置在衬底之间的第一和第二 第一互补数据线对的数据线。 第一预充电晶体管包括第一源极/漏极区域，在第一方向上从第一源极/漏极区域移位的衬底中的第三源极/漏极区域以及设置在衬底上的第一和第三预充电晶体管栅极电极 源极/漏极区域。 第二预充电晶体管包括第二源极/漏极区域，在第一方向上从第二源极/漏极区域移位的衬底中的第四源极/漏极区域，以及第二预充电晶体管栅极电极，位于第二和第四 源极/漏极区域。 预充电电压总线导体设置在衬底上并电耦合到第三和第四源极/漏极区域。

公开(公告)号：KR100454123B1

公开(公告)日：2004-10-26

申请号：KR1020010076944

申请日：2001-12-06

Applicant: 삼성전자주식회사

Inventor： 장성진 ,  전영현 ,  강창만

IPC: G11C5/02

CPC classification number: G11C5/063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

Abstract translation: 集成电路包括具有与衬底集成的电路的衬底。 切换电路可选择性地操作以配置到衬底上的替代镜像焊盘的信号路径。 第一和第二信号路径中的至少一个可以包括串联在开关电路和其相应的焊盘之间的缓冲器。

公开(公告)号：KR1020040011958A

公开(公告)日：2004-02-11

申请号：KR1020020045287

申请日：2002-07-31

Applicant: 삼성전자주식회사

Inventor： 강창만 ,  김정열

IPC: G11C11/40

CPC classification number: G11C7/1066 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072

Abstract: PURPOSE: A data output circuit of a synchronous semiconductor memory device is provided to minimize junction loading and interconnection loading and data skew. CONSTITUTION: According to the data output circuit of a synchronous semiconductor memory device comprising a data output multiplexer having a wave pipeline structure, every output port of two register output selection switches is connected to a multiplexing output line through a single line, by forming output part active regions of adjacent register output selection switches(S1,S2,S3,S4,S5,S8,S9,S10,S12,S13,S16) in common, in order to reduce junction loading of the multiplexing output line connected to lines connected to output ports of register output selection switches in the above data output multiplexer in common. The above register output selection switches are constituted with a CMOS transmission gate respectively.

Abstract translation: 目的：提供同步半导体存储器件的数据输出电路以最小化负载和互连负载以及数据偏移。 构成：根据包括具有波形流水线结构的数据输出多路复用器的同步半导体存储器件的数据输出电路，两个寄存器输出选择开关的每个输出端口通过一条线连接到复用输出线，通过形成输出部分 相邻寄存器输出选择开关（S1，S2，S3，S4，S5，S8，S9，S10，S12，S13，S16）的有源区域是为了减少与连接到 上述数据输出多路复用器中的寄存器输出选择开关的输出端口是共同的。 上述寄存器输出选择开关分别由CMOS传输门构成。

公开(公告)号：KR1020040017691A

公开(公告)日：2004-02-27

申请号：KR1020020050117

申请日：2002-08-23

Applicant: 삼성전자주식회사

Inventor： 박윤식 ,  강창만

IPC: G11C5/02

CPC classification number: H04L25/028 ,  H04L25/0278 ,  H04L25/0292

Abstract: PURPOSE: A layout of a semiconductor IC having a termination circuit is provided to reduce a size of the semiconductor IC by arranging efficiently a pad, an output buffer, and the termination circuit. CONSTITUTION: A semiconductor IC having a termination circuit includes one pad(101), a transmitter, and a termination circuit(160a,160b). The pad(101) is connected to a bus line. The transmitter is used for transmitting a signal of an internal circuit to the outside through the pad(101). The termination circuit(160a,160b) is used for terminating the bus line. The pad(101) is surrounded by the transmitter and the termination circuit(160a,160b). The pad(101) is formed with a square pad having the first to the fourth sides.

Abstract translation: 目的：提供具有终端电路的半导体IC的布局，以有效地布置焊盘，输出缓冲器和终端电路来减小半导体IC的尺寸。 构成：具有终端电路的半导体IC包括一个焊盘（101），发送器和终端电路（160a，160b）。 焊盘（101）连接到总线。 发射机用于通过焊盘（101）将内部电路的信号传输到外部。 终端电路（160a，160b）用于终止总线。 垫（101）由发射器和终端电路（160a，160b）包围。 垫（101）形成有具有第一至第四侧的正方形垫。

公开(公告)号：KR100448901B1

公开(公告)日：2004-09-16

申请号：KR1020020050117

申请日：2002-08-23

Applicant: 삼성전자주식회사

Inventor： 박윤식 ,  강창만

IPC: G11C5/02

CPC classification number: H04L25/028 ,  H04L25/0278 ,  H04L25/0292

Abstract: A semiconductor integrated circuit includes at least one pad coupled to a bus line, a transmitter for transmitting a signal from an internal circuit to the outside through the pad, and a termination circuit for terminating the bus line. The transmitter and the termination circuit are disposed to surround the pad, reducing a size of the semiconductor integrated circuit.

Abstract translation: 半导体集成电路包括耦合到总线的至少一个焊盘，用于通过焊盘将来自内部电路的信号传输到外部的发射器以及用于终止总线的终端电路。 发射器和终端电路被设置为包围焊盘，从而减小了半导体集成电路的尺寸。

公开(公告)号：KR1020040014742A

公开(公告)日：2004-02-18

申请号：KR1020020047380

申请日：2002-08-10

Applicant: 삼성전자주식회사

Inventor： 강창만

IPC: G11C7/12

CPC classification number: G11C7/1048 ,  G11C7/1006

Abstract: PURPOSE: An equalization/precharge circuit and a semiconductor memory device comprising the same are provided to improve signal transmission characteristics through input/output line pair. CONSTITUTION: The equalization/precharge circuit are connected to a bit line and a complementary bit line connected to a memory cell array through a column selection transistor, and they equalize and precharge a data line and a complementary data line arranged in parallel. An equalization transistor(EQ1) equalizes the data line and the complementary data line. The first precharge transistor(PCH1) precharges the data line to a fixed voltage level. The second precharge transistor(PCH2) precharges the complementary data line to the voltage level. A gate of the equalization transistor and a gate of the first precharge transistor and a gate of the second precharge transistor are connected in a T shape each other.

Abstract translation: 目的：提供均衡/预充电电路和包括该均衡/预充电电路的半导体存储器件，以通过输入/输出线对提高信号传输特性。 构成：均衡/预充电电路通过列选择晶体管连接到位线和与存储单元阵列连接的互补位线，并且它们对并行布置的数据线和互补数据线进行均衡和预充电。 均衡晶体管（EQ1）使数据线和互补数据线均衡。 第一预充电晶体管（PCH1）将数据线预充电到固定的电压电平。 第二预充电晶体管（PCH2）将互补数据线预充电到电压电平。 均衡晶体管的栅极和第一预充电晶体管的栅极和第二预充电晶体管的栅极彼此以T形连接。

公开(公告)号：KR1020030046715A

公开(公告)日：2003-06-18

申请号：KR1020010076944

申请日：2001-12-06

Applicant: 삼성전자주식회사

Inventor： 장성진 ,  전영현 ,  강창만

IPC: G11C5/02

CPC classification number: G11C5/063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor IC circuit and a module including the same are provided to minimize the number of crossing wires by changing external signals of TTL-level to internal signals of CMOS-level and switching the internal signals of CMOS-level to internal circuits. CONSTITUTION: A semiconductor device includes a plurality of bonding pads(1000,1100), a plurality of input buffer circuits(BUF1,BUF2), and a plurality of multiplexer circuits(MUX1,MUX2). The bonding pads are connected to external electrodes in order to receive TTL-level external signals. The input buffer circuits are connected to the bonding pads in order to output CMOS-level internal signals corresponding to the external signals. The multiplexer circuits are used for receiving the output signals of the input buffer circuits and switching the inputted signals in response to control signals. The input signals applied to the bonding pads are transmitted to the first internal circuit(1200) when the semiconductor device is packaged by the first package. The input signals applied to the bonding pads are transmitted to the second internal circuit(1300) when the semiconductor device is packaged by the second package.

Abstract translation: 目的：提供半导体IC电路及包含该半导体IC电路的模块，通过将TTL电平的外部信号改变为CMOS电平的内部信号并将CMOS电平的内部信号切换到内部电路来最小化交叉线的数量。 构成：半导体器件包括多个接合焊盘（1000,1100），多个输入缓冲电路（BUF1，BUF2）和多个多路复用器电路（MUX1，MUX2）。 接合焊盘连接到外部电极，以便接收TTL电平的外部信号。 输入缓冲器电路连接到接合焊盘，以输出对应于外部信号的CMOS电平内部信号。 多路复用器电路用于接收输入缓冲电路的输出信号，并响应控制信号切换输入信号。 当半导体器件被第一封装封装时，施加到接合焊盘的输入信号被传输到第一内部电路（1200）。 当半导体器件被第二封装封装时，施加到接合焊盘的输入信号被传输到第二内部电路（1300）。