中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.018 seconds)

    저항과 콘덴서를 동시에 집적시키는 방법 및 반도체 소자의 구조
    6.
    发明授权
    저항과 콘덴서를 동시에 집적시키는 방법 및 반도체 소자의 구조 失效
    电容器电容器的集成方法和半导体器件的结构

    公开(公告)号：KR1019910009613B1

    公开(公告)日：1991-11-23

    申请号：KR1019880016961

    申请日：1988-12-19

    Applicant: 삼성전자주식회사

    Inventor： 김현수 ,  강현순 ,  권철순 ,  김명성

    IPC: H01L27/00

    Abstract: The method for integrating the resistor in semiconductor device comprises the steps of: forming a epitaxial layer (2) on p-type silicon substrate (1), followed by forming a oxide film (3), nitride film (4) in sequence; removing a fixed part of (4) and (3) by photo lighography processing; depositing the polycrystalline silicon (7) and inserting the polycrystalline silicon into the semiconductor device by lithography processing; forming a contact hole and metal interconnection line to connect the metal electrode (21) with polycrystalline silicon inserted into device. This method has advantage of decreasing the chip size and contact resistance by using the barrier metal.

    Abstract translation: 用于将电阻器集成在半导体器件中的方法包括以下步骤：在p型硅衬底（1）上形成外延层（2），然后依次形成氧化膜（3），氮化膜（4） 通过照相光刻处理去除（4）和（3）的固定部分; 沉积多晶硅（7）并通过光刻处理将多晶硅插入半导体器件; 形成接触孔和金属互连线，以将金属电极（21）与插入设备的多晶硅连接。 该方法具有通过使用阻挡金属来降低芯片尺寸和接触电阻的优点。

    I2L소자및그제조방법
    7.
    发明授权
    I2L소자및그제조방법 失效
    I2L器件及其制造方法

    公开(公告)号：KR1019930004299B1

    公开(公告)日：1993-05-22

    申请号：KR1019900019299

    申请日：1990-11-28

    Applicant: 삼성전자주식회사

    Inventor： 김현수 ,  강현순 ,  김명성 ,  임순권

    IPC: H01L29/735

    Abstract: The TIL (integrated injection logic) device for improving an operation speed and reducing the power consumption comprises a P substrate (50) having an N+ buried layer (52), an n epitaxial layer (54) and a P+ diffusion region (66), first to third field oxide films (64a,64b,64c) formed on the diffusion region (66) and epitaxial layer (54), P active regions (72,74) having a P active region (76) and a n active region (86) adjacent the films (64a,64b) and separated from each other, P active regions (72,75) having n active regions (88,90), a number of electrodes (76) having a laminated structure of polysilicon and silicide layers, and metallic electrodes (98,99) contacted with the active regions (72,74,75,76).

    Abstract translation: 用于提高操作速度并降低功耗的TIL（集成注入逻辑）装置包括具有N +掩埋层（52），n外延层（54）和P +扩散区（66）的P基板（50） 形成在扩散区（66）和外延层（54）上的第一至第三场氧化膜（64a，64b，64c），具有P有源区（76）和有源区（86）的P有源区（72,74） ）与膜（64a，64b）相邻并且彼此分离，具有n个有源区（88,90）的P个有源区（72,75），具有多晶硅和硅化物层的层叠结构的多个电极（76） 和与活性区（72,74,75,76）接触的金属电极（98,99）。

    자기정합된 바이폴라 트랜지스터의 제조방법
    8.
    发明授权
    자기정합된 바이폴라 트랜지스터의 제조방법 失效
    自匹配双极晶体管的制造方法

    公开(公告)号：KR1019920010063B1

    公开(公告)日：1992-11-13

    申请号：KR1019890004059

    申请日：1989-03-30

    Applicant: 삼성전자주식회사

    Inventor： 김현수 ,  권철순 ,  강현순 ,  김명성

    IPC: H01L21/04 ,  H01L29/70

    Abstract: A self-aligned bipolar transistor is manufactured by (A) forming successively high and low concentration layers (2,3), which contain a second conductive impurity, on the first conductive silicon substrate (1), (B) forming isolation area by photoetching, (C) forming collector area and field oxide film to separate acitve area and inactive area, (D) forming successively polysilicon film (18) and oxide film (20), (E) removing the films (18,20) by photoetching to form an aperture on emitter and collector areas, (F) forming nitride film (25) on the side walls of the films (18,20), (G) forming polysilicon layer (27), (H) forming base area, and (I) forming emitter area thereon using bove nitride side wall.

    Abstract translation: （A）在第一导电硅衬底（1）上形成连续的含有第二导电杂质的高浓度低浓度层（2,3），（B）通过光刻形成隔离区域来制造自对准双极晶体管 （C）形成集电极区域和场氧化膜以分离区域和非活性区域，（D）依次形成多晶硅膜（18）和氧化物膜（20），（E）通过光刻去除膜（18,20） 在发射极和集电极区域上形成孔，（F）在形成多晶硅层（27）的膜（18,20）的侧壁上形成氮化物膜（25），形成基底区域的（H）和（ I）在其上用氮化物侧壁形成发射极区域。

    반도체장치의 제조방법
    9.
    发明授权
    반도체장치의 제조방법 失效
    半导体器件的制造方法

    公开(公告)号：KR1019920007365B1

    公开(公告)日：1992-08-31

    申请号：KR1019900000627

    申请日：1990-01-19

    Applicant: 삼성전자주식회사

    Inventor： 강현순

    IPC: H01L29/735

    Abstract: The method for integrating a high voltage transistor and a general transistor in one chip comprises the steps of forming an N+ buried layer (3) into a Si substrate (1) to grow an epitaxial layer (4) over the whole substrate (1), ion-implanting and diffusing an N impurities to form N+ buried layers (51',52'), forming a P+ buried layer (6) for isolating between the devices by ion-implanting and diffusing P impurities, forming a second epitaxial layer (7) on the whole substrate, ion-implanting and diffusing N impurities to form N+ collector regions (81',82'), forming a P+ buried layer (9) as a second isolation area by ion-implanting and diffusing P impurities and forming base and emitter regions into the epitaxial layer (7).

    Abstract translation: 用于将高压晶体管和一般晶体管集成在一个芯片中的方法包括以下步骤：在整个衬底（1）上形成N衬底（1）以在外延层（4）上生长外延层（4） 离子注入和扩散N个杂质以形成N +掩埋层（51'，52'），形成用于通过离子注入和扩散P杂质在器件之间隔离的P +掩埋层（6），形成第二外延层 ）在整个衬底上，离子注入和扩散N个杂质以形成N +集电极区域（81'，82'），通过离子注入和扩散P杂质形成P +掩埋层（9）作为第二隔离区域并形成基底 和发射极区进入外延层（7）。

Patent Agency Ranking