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2.发明授权측정의 신뢰도를 향상시킬 수 있는 측정용 패턴을구비하는 반도체장치 및 측정용 패턴을 이용한반도체장치의 측정방법 有权具有提高测量可靠性的测量图案的半导体器件和使用测量图案测量半导体器件的方法
公开(公告)号：KR100546330B1
公开(公告)日：2006-01-26
申请号：KR1020030035603
申请日：2003-06-03
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: 측정용 패턴을 개선하여 측정의 신뢰도를 향상시킬 수 있는 측정용 패턴을 구비하는 반도체장치 및 이를 이용한 반도체장치의 측정방법이 개시된다. 본 발명에 따른 측정용 패턴을 구비하는 반도체장치는, 반도체 집적회로가 형성되는 칩영역과 상기 칩영역을 둘러싸는 스크라이브영역을 포함하는 반도체기판; 상기 스크라이브영역 내의 상기 반도체기판의 표면에 빈 공간의 형태로 형성되며, 계측설비의 측정용 빔이 투사되는 빔영역이 포함될 수 있도록 일정한 표면 단면적을 갖는 측정용 패턴; 및 상기 측정용 패턴의 내부에, 상기 측정용 패턴의 빈 공간의 표면 단면적을 감소, 예를 들어 빔영역의 표면 단면적 대비 더미 패턴의 표면 단면적의 비율이 5% 내지 15%가 될 수 있도록 더미 패턴을 포함한다.
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3.发明公开불 휘발성 메모리 소자의 스플릿 게이트 전극 형성방법 无效用于形成栅极电极的栅极电极，用于在栅极电极的控制栅下形成栅极氧化层的方法，其具有适用于控制栅极的高电压并且使氧化物层与控制栅极接触的电极的平滑电极隧道效应
公开(公告)号：KR1020050020507A
公开(公告)日：2005-03-04
申请号：KR1020030058520
申请日：2003-08-23
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: PURPOSE: A method for forming a split gate electrode of an NVM(non-volatile memory) device is provided to make a gate oxide layer under a control gate of a split gate electrode have a withstand voltage with respect to a high voltage applied to the control gate and make the oxide layer in contact with a control gate sidewall smoothen a tunneling effect of electrons by making the oxide layers existing between the control gate and a floating gate and under the control gate have different thicknesses. CONSTITUTION: After a nitride layer pattern selectively exposing a polysilicon layer is formed, a spacer oxide layer with a uniform thickness is formed. An etch-back process is performed to form a spacer and a split polysilicon layer pattern and a source line is formed in the opening of the nitride layer pattern. After the exposed nitride layer pattern and the exposed polysilicon layer pattern are etched to form a split floating gate, the gate oxide layer existing in a region except the split floating gate is etched to a degree that a substrate(100) is not exposed. The second gate oxide layer with a uniform thickness is formed on the resultant structure.
Abstract translation: 目的：提供一种用于形成NVM（非易失性存储器）器件的分离栅电极的方法，以使分裂栅电极的控制栅极下方的栅极氧化层具有相对于施加到该栅极电极的高电压的耐受电压 控制栅极，并使氧化层与控制栅极侧壁接触，通过使控制栅极和浮动栅极之间以及控制栅极下方的氧化物层具有不同的厚度来平滑电子的隧道效应。 构成：在形成选择性地暴露多晶硅层的氮化物层图案之后，形成厚度均匀的间隔氧化物层。 执行回蚀处理以形成间隔物和分裂多晶硅层图案，并且在氮化物层图案的开口中形成源极线。 在暴露的氮化物层图案和暴露的多晶硅层图案被蚀刻以形成分离浮置栅极之后，存在于除了分离的浮置栅极之外的区域中的栅极氧化物层被蚀刻到基板（100）不暴露的程度。 在所得结构上形成具有均匀厚度的第二栅极氧化物层。
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公开(公告)号：KR1020030045265A
公开(公告)日：2003-06-11
申请号：KR1020010075681
申请日：2001-12-01
Applicant: 삼성전자주식회사
IPC: H01L21/8242
Abstract: PURPOSE: A method for forming a capacitor of a semiconductor device is provided to be capable of improving the stability of a capacitor dielectric layer by using an ALD(Atomic Layer Deposition) method. CONSTITUTION: A lower electrode(110) for capacitor is formed on a lower interlayer dielectric(100) of a semiconductor substrate. An interlayer dielectric pattern(120) is formed on the resultant structure. At this time, the first opening portion(125) is formed in the interlayer dielectric pattern(120) for exposing the upper portion of the lower electrode(110). A capacitor dielectric(130) is selectively formed on the resultant structure by using an ALD method at the temperature of 300-400°C. An upper electrode(140) for capacitor is formed on the capacitor dielectric(130) of the first opening portion for filling the first opening portion.
Abstract translation: 目的：提供一种用于形成半导体器件的电容器的方法，其能够通过使用ALD（原子层沉积）方法来提高电容器电介质层的稳定性。 构成：用于电容器的下电极（110）形成在半导体衬底的下层间电介质（100）上。 在所得结构上形成层间电介质图案（120）。 此时，第一开口部（125）形成在用于露出下电极（110）的上部的层间电介质图案（120）中。 通过使用ALD法在300-400℃的温度下，在所得结构上选择性地形成电容器电介质（130）。 用于电容器的上电极（140）形成在用于填充第一开口部分的第一开口部分的电容器电介质（130）上。
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公开(公告)号：KR1020000020577A
公开(公告)日：2000-04-15
申请号：KR1019980039246
申请日：1998-09-22
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L27/10894 , H01L27/10814 , H01L27/10852 , H01L27/10882
Abstract: PURPOSE: An MDL(merged DRAM and logic) and manufacturing method are provided to enhance the MDL by ensuring sufficient photo margin in wiring, and to enhance the reliability of the process by preventing the process failure generated during forming a contact hole. CONSTITUTION: A merged DRAM and logic comprises a nth layer insulation film formed on a semiconductor substrate(100), a first metal wiring(128) formed on the nth insulation film, a (n+1)th layer insulation film formed on the nth insulation film, a first metal wiring formed on the (n+1)th layer insulation film, and a second metal wiring formed on the (n+1)th layer insulation film. The first metal wiring is formed any region except memory cell region(A). The first metal wiring is formed in the memory cell region. The second metal wiring is formed in the any region.
Abstract translation: 目的：提供MDL（合并DRAM和逻辑）和制造方法，以通过确保布线中的足够的照片余量来增强MDL，并且通过防止在形成接触孔期间产生的处理故障来提高工艺的可靠性。 构成：合并的DRAM和逻辑包括形成在半导体衬底（100）上的第n层绝缘膜，形成在第n绝缘膜上的第一金属布线（128），形成在第n绝缘膜上的第（n + 1）层绝缘膜 绝缘膜，形成在第（n + 1）层绝缘膜上的第一金属布线和形成在第（n + 1）层绝缘膜上的第二金属布线。 除了存储单元区域（A）之外，第一金属布线形成为任何区域。 第一金属布线形成在存储单元区域中。 第二金属布线形成在任何区域。
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Patent Agency Ranking
公开(公告)号：KR1019990039156A
公开(公告)日：1999-06-05
申请号：KR1019970059140
申请日：1997-11-11
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 본 발명은 반도체 소자의 패드에 관한 것으로, 통상의 패드 크기와 동일한 면적에 금속배선간 연결 영역과 소자의 특성 평가를 위한 프로빙 영역을 구분하여 패드를 형성하되, 최종금속배선을 제외한 금속배선층과 비아 영역이 상기 금속배선간 연결영역에만 형성되도록 하여, 반도체 소자의 특성 평가를 위한 멀티-프로빙시 스트래스에 의한 층간절연막층의 크랙 등 불량이 방지되도록 하였다.
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公开(公告)号：KR1020100068005A
公开(公告)日：2010-06-22
申请号：KR1020080126642
申请日：2008-12-12
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/10864 , H01L27/10841 , H01L27/10882 , H01L27/10891
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce manufacturing costs by forming an impurity layer on a semiconductor substrate. CONSTITUTION: An epitaxial layer is formed on a semiconductor substrate(110). A body is formed by etching the epitaxial layer after forming the epitaxial layer with a plurality of impurities by implanting ions. The body is vertical to the semiconductor substrate and includes a storage body(1050) comprised of a plurality of impurity layers and an access body(1070) formed on the storage body. Common lines(200) correspond to the storage body and are arranged while interposing the body. Word lines(400) are formed on the common lines in parallel and correspond to the access body.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过在半导体衬底上形成杂质层来降低制造成本。 构成：在半导体衬底（110）上形成外延层。 在通过注入离子形成具有多种杂质的外延层之后，通过蚀刻外延层形成主体。 本体与半导体衬底垂直，并且包括由多个杂质层组成的存储体（1050）和形成在存储体上的存取体（1070）。 公共线（200）对应于存储体并且在插入身体的同时被布置。 字线（400）平行地形成在公共线上并对应于存取体。
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公开(公告)号：KR1020080028129A
公开(公告)日：2008-03-31
申请号：KR1020060093518
申请日：2006-09-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/2436 , G11C16/02 , H01L27/2463
Abstract: A non-volatile memory device is provided to increase the electron mobility of a channel region by disposing an active region in a direction to increase the electron mobility. An active region(10) is disposed in a substrate(1) having a first surface azimuth in a first lattice direction to increase the electron mobility. A flash memory transistor(30) is formed in the active region in a second lattice direction. The active region is formed in the first lattice direction along the surface azimuth of the substrate, and the flash memory transistor is disposed in the second lattice direction at an angle of 45 degrees to the first lattice direction to increase an effective channel width of a channel region.
Abstract translation: 提供非易失性存储器件以通过在增加电子迁移率的方向上设置有源区来增加沟道区的电子迁移率。 有源区域（10）设置在具有第一晶格方向的第一表面方位的衬底（1）中以增加电子迁移率。 闪存晶体管（30）在第二格子方向的有源区域中形成。 有源区域沿着衬底的表面方位沿第一晶格方向形成，并且闪存晶体管以与第一晶格方向成45度角的第二晶格方向设置，以增加沟道的有效沟道宽度 地区。
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公开(公告)号：KR100809341B1
公开(公告)日：2008-03-05
申请号：KR1020070010703
申请日：2007-02-01
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L27/02 , H01L23/36
CPC classification number: H01L27/24 , G11C13/0004 , G11C2213/79
Abstract: A nonvolatile memory device using a resistive element and a manufacturing method thereof are provided to implement high integration degree by using heat sink patterns. Plural variable resistance patterns(GST) are formed on a semiconductor substrate(110). Plural heat sink patterns(170) are formed at the same level as the variable resistance pattern. The heat sink patterns are connected to a ground voltage line(144). The ground voltage line is extended to a first direction. The heat sink pattern is extended to the first direction on the ground voltage line. The heat sink pattern includes a first sub heat sink pattern and a second sub heat sink pattern. The first sub heat sink pattern is formed on the ground voltage line to be extended to the first direction. The second sub heat sink pattern is extended to a second direction to be intersected with the first direction.
Abstract translation: 提供使用电阻元件的非易失性存储器件及其制造方法，以通过使用散热片图案实现高集成度。 多个可变电阻图案（GST）形成在半导体衬底（110）上。 多个散热片图案（170）形成在与可变电阻图案相同的水平。 散热片图案连接到地电压线（144）。 接地电压线延伸到第一方向。 散热器模式延伸到地电压线上的第一个方向。 散热器模式包括第一子散热器模式和第二子散热器模式。 第一副散热图案形成在接地电压线上以延伸到第一方向。 第二副散热图案延伸到与第一方向交叉的第二方向。
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