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公开(公告)号：KR1020140001578A
公开(公告)日：2014-01-07
申请号：KR1020120069473
申请日：2012-06-27
Applicant: 삼성전자주식회사
IPC: H01L21/00
CPC classification number: G06F17/5072 , G06F17/50 , G06F17/5077 , G06F17/5081 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/6681
Abstract: Provided are a method for designing an integrated semiconductor circuit, the integrated semiconductor circuit according to the method, and a manufacturing method thereof capable of minimizing parasitic capacitance generated by an overhead of a gate line. The method for designing the integrated semiconductor circuit comprises a step for performing pre-simulation for the integrated semiconductor circuit; a step for designing a layout including cells and wirings in response to the integrated semiconductor circuit; a step for automatically arranging a cutting area by using an arrangement process; and a step for performing post-simulation based on the layout. The cutting area electrically cuts a conductive line between two device areas. The conductive line is extended through the two device areas in the layout. [Reference numerals] (AA) Start; (BB) End; (S110) Perform pre-simulation; (S130) Design a layout (DRC/LVS); (S150) Arrange a cutting area by using an arrangement process; (S170) Perform post-simulation
Abstract translation: 提供一种用于设计集成半导体电路的方法，根据该方法的集成半导体电路及其制造方法，其能够最小化由栅极线的开销产生的寄生电容。 集成半导体电路的设计方法包括对集成半导体电路进行预仿真的步骤; 响应于集成半导体电路设计包括单元和布线的布局的步骤; 通过使用布置处理来自动布置切割区域的步骤; 以及基于布局进行后仿真的步骤。 切割区域在两个设备区域之间电切割导线。 导线延伸穿过布局中的两个设备区域。 （附图标记）（AA）开始; （BB）结束; （S110）执行预仿真; （S130）设计布局（DRC / LVS）; （S150）使用安排程序安排切割区域; （S170）执行后仿真
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