公开(公告)号：KR1020040020651A

公开(公告)日：2004-03-09

申请号：KR1020020052308

申请日：2002-08-31

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  박재현

IPC: H01L21/28

Abstract: PURPOSE: A contact of a semiconductor device and a method for forming the same are provided to be capable of enhancing gap-fill margin at filling a conductive layer in a contact hole. CONSTITUTION: The first photoresist pattern is formed on a semiconductor substrate(10) having an oxide layer(20). The first etching portion is formed by selectively etching the oxide layer using the first photoresist pattern. The second photoresist pattern is formed by flowing the first photoresist pattern. Then, the second etching portion is formed by wet-etching of the first etching portion using the second photoresist pattern. A contact hole is formed by dry-etching the second and first etching portion using the first photoresist pattern. A contact is then formed by filling a conductive layer in the contact hole.

Abstract translation: 目的：提供半导体器件的接触及其形成方法，以便能够在填充接触孔中的导电层时增加间隙填充余量。 构成：第一光致抗蚀剂图案形成在具有氧化物层（20）的半导体衬底（10）上。 通过使用第一光致抗蚀剂图案选择性地蚀刻氧化物层来形成第一蚀刻部分。 通过使第一光致抗蚀剂图案流动来形成第二光致抗蚀剂图案。 然后，通过使用第二光致抗蚀剂图案湿法蚀刻第一蚀刻部分来形成第二蚀刻部分。 通过使用第一光致抗蚀剂图案对第二和第一蚀刻部分进行干蚀刻来形成接触孔。 然后通过在接触孔中填充导电层形成接触。

公开(公告)号：KR1020030006240A

公开(公告)日：2003-01-23

申请号：KR1020010041939

申请日：2001-07-12

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  윤석훈 ,  박재현

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A method for forming a fuse is provided to enhance efficiency of a fabrication process by omitting a process for removing a fence. CONSTITUTION: A metal barrier and a metal layer are sequentially on a substrate(30). A metal line pattern is formed by etching sequentially the metal barrier and the metal layer of the first predetermined region. An insulating layer is continuously formed on the metal line pattern and the exposed substrate(30). The insulating layer of the second predetermined region is etched by using an etch gas including fluoro-carbon compound and fluoro-silicon compound. A metal line pattern having an insulating layer residue(36a) of the second predetermined region is exposed to define a fuse pattern region by etching the insulating layer of the second predetermined region. A fuse pattern(38) is formed by removing the metal layer from the metal line pattern of the fuse pattern region. A protective layer(40) is formed on an entire substrate of the resultant structure.

Abstract translation: 目的：提供一种用于形成保险丝的方法，以通过省略除去栅栏的过程来提高制造过程的效率。 构成：金属屏障和金属层顺序地在基片（30）上。 通过依次蚀刻第一预定区域的金属阻挡层和金属层形成金属线图案。 在金属线图案和暴露的基板（30）上连续地形成绝缘层。 通过使用包括氟碳化合物和氟 - 硅化合物的蚀刻气体来蚀刻第二预定区域的绝缘层。 通过蚀刻第二预定区域的绝缘层，露出具有第二预定区域的绝缘层残留物（36a）的金属线图案以限定熔丝图案区域。 通过从熔丝图案区域的金属线图案去除金属层来形成熔丝图案（38）。 在所得结构的整个基板上形成保护层（40）。

公开(公告)号：KR1020010017558A

公开(公告)日：2001-03-05

申请号：KR1019990033139

申请日：1999-08-12

Applicant: 삼성전자주식회사

Inventor： 심광보 ,  고동환 ,  서정근 ,  이영우

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a contact between devices is provided to eliminate an isolating problem caused by misalignment of a contact plug, by forming a contact pad while forming a bit line. CONSTITUTION: The first insulating layer(212) is deposited on a semiconductor substrate having the first contact pad(210). The first insulating layer is etched to expose the first contact pad, and the first contact hole is formed. The first conductive layer(216) is formed on the first insulating layer to fill the first contact hole. The second conductive layer(218) is deposited on the first conductive layer. The second and first conductive layers are etched to expose the first insulating layer through a photo process, and a bit line(220) and the second contact pad(222) are formed. The second insulating layer(224) is deposited on the entire substrate. The second insulating layer is etched to expose an upper surface of the second contact pad, and the second contact hole is formed. The third conductive layer(228) is deposited on the second insulating layer to fill the second contact hole.

Abstract translation: 目的：提供一种用于制造器件之间的接触的方法，以通过在形成位线的同时形成接触焊盘来消除由接触插塞的未对准引起的隔离问题。 构成：第一绝缘层（212）沉积在具有第一接触焊盘（210）的半导体衬底上。 蚀刻第一绝缘层以露出第一接触焊盘，并且形成第一接触孔。 第一导电层（216）形成在第一绝缘层上以填充第一接触孔。 第二导电层（218）沉积在第一导电层上。 蚀刻第二和第一导电层以通过光刻工艺暴露第一绝缘层，并且形成位线（220）和第二接触焊盘（222）。 第二绝缘层（224）沉积在整个基板上。 蚀刻第二绝缘层以暴露第二接触焊盘的上表面，并且形成第二接触孔。 第三导电层（228）沉积在第二绝缘层上以填充第二接触孔。

公开(公告)号：KR1019990065174A

公开(公告)日：1999-08-05

申请号：KR1019980000343

申请日：1998-01-09

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  정규찬 ,  이휘건

IPC: H01L21/312

Abstract: 본 발명은 에스오지막(Spin On Glass film)이 형성된 반도체기판 상에 평탄화공정으로서 에치백(Etch Back)공정을 수행한 후 상기 에치백공정의 수행에 의해서 상기 에스오지막 상에 존재하는 폴리머(Polymer)를 용이하게 제거할 수 있는 반도체장치 제조용 에스오지막 형성방법에 관한 것이다.
본 발명은, 특정막이 형성된 반도체기판 상에 에스오지막을 형성하는 단계, 상기 반도체기판 상의 에스오지막을 반응가스를 사용하여 에치백하는 단계 및 상기 에치백에 의해서 상기 반도체기판 상에 존재하는 폴리머를 산소가스 및 메탄테트라플루라이드(CF
4 )가스를 사용하여 플라즈마 식각하는 단계를 구비하여 이루어지는 것을 특징으로 한다.
따라서, 에치백된 에스오지막에 균열이 발생되는 것을 방지하며, 에스오지막 상에 존재하는 폴리머를 용이하게 제거할 수 있는 효과가 있다.

公开(公告)号：KR100524969B1

公开(公告)日：2005-10-31

申请号：KR1020030039129

申请日：2003-06-17

Applicant: 삼성전자주식회사

Inventor： 남진택 ,  고동환

IPC: H01L21/82

Abstract: 퓨즈 컷팅홀 형성을 위한 리페어 식각을 패드 식각과 동시에 행하는 데 있어서, 폴리머 부산물 생성을 억제하는 동시에 퓨즈의 손상 없이 퓨즈 상면 위의 절연층 두께를 낮추기 위하여 2 단계 식각 공정을 행한다. 제1 식각 단계에서는 SF
6 가스를 포함하는 제1 식각 가스를 사용하여 퓨즈 상부 및 본딩 패드 상부의 절연층을 일부 제거한다. 제2 식각 단계에서는 퓨즈를 구성하는 텅스텐 실리사이드층의 손상을 방지할 수 있도록 SF
6 가스를 포함하지 않는 제2 식각 가스를 사용하여 본딩 패드 상부의 절연층을 목표량까지 식각한다.

公开(公告)号：KR1020030061878A

公开(公告)日：2003-07-23

申请号：KR1020020001876

申请日：2002-01-12

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  김재필 ,  김동욱

IPC: H01L21/28

Abstract: PURPOSE: A method for fabricating the metal interconnection of a semiconductor device is provided to control the corrosion of the metal interconnection by effectively eliminating the residue containing chlorine radicals while using the plasma generated by H2N2 gas. CONSTITUTION: A conductive layer for metal interconnection is formed on a substrate. A photoresist layer pattern is formed on the conductive layer. Etching gas including chlorine is supplied to selectively etch the conductive layer in an etch chamber by using the photoresist pattern as an etch mask. The chlorine residue is eliminated in an H2N2 gas atmosphere.

Abstract translation: 目的：提供一种用于制造半导体器件的金属互连的方法，以通过在使用由H 2 N 2气体产生的等离子体的同时有效地除去含有氯自由基的残留物来控制金属互连的腐蚀。 构成：在基板上形成用于金属互连的导电层。 在导电层上形成光致抗蚀剂图案。 提供包括氯的蚀刻气体，以通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地蚀刻蚀刻室中的导电层。 在H2N2气体气氛中除去氯残留物。

公开(公告)号：KR1020020047486A

公开(公告)日：2002-06-22

申请号：KR1020000075940

申请日：2000-12-13

Applicant: 삼성전자주식회사

Inventor： 고동환 ,  김홍일 ,  김재필

IPC: H01L21/3065

Abstract: PURPOSE: A method for etching a metal layer of a semiconductor device is provided to obtain a desired excellent profile, to reduce micro loading effect in etching the metal layer and to prevent a bridge phenomenon caused by residual photoresist, by preventing an undercut phenomenon under an upper barrier layer. CONSTITUTION: A metal layer in which a lower barrier layer(102), an aluminum layer and the upper barrier layer are sequentially stacked, is formed on a semiconductor substrate(100). Photoresist is applied on the upper barrier layer to form a photoresist pattern(108). Mixed gas of Cl2 and BCl3 is used as etching gas in an inductively coupled plasma apparatus while the photoresist pattern is used as a mask and the ratio of bias power to bottom power is 1.5-2:1 so that a predetermined depth of the aluminum layer is etched from the upper barrier layer and a portion under the upper barrier layer. The rest of the aluminum layer except the etched aluminum layer is etched by using the photoresist pattern as a mask. The lower barrier layer and a part of the semiconductor substrate under the lower barrier layer are etched by using the photoresist pattern as a mask.

Abstract translation: 目的：提供一种用于蚀刻半导体器件的金属层的方法以获得期望的优异外形，以减少在蚀刻金属层时的微负载效应，并且通过防止由于残留光致抗蚀剂引起的底切现象而防止残留光致抗蚀剂引起的桥接现象 上阻隔层。 构成：在半导体衬底（100）上形成下阻挡层（102），铝层和上阻挡层依次层叠的金属层。 将光刻胶施加在上阻挡层上以形成光致抗蚀剂图案（108）。 使用Cl 2和BCl 3的混合气体作为电感耦合等离子体装置中的蚀刻气体，同时将光致抗蚀剂图案用作掩模，并且偏压功率与底部功率的比为1.5-2:1，使得铝层的预定深度 从上阻挡层和上阻挡层下面的部分蚀刻。 除了蚀刻的铝层之外的铝层的其余部分通过使用光致抗蚀剂图案作为掩模进行蚀刻。 通过使用光致抗蚀剂图案作为掩模来蚀刻下阻挡层和下阻挡层下的半导体衬底的一部分。

公开(公告)号：KR1020020030460A

公开(公告)日：2002-04-25

申请号：KR1020000061096

申请日：2000-10-17

Applicant: 삼성전자주식회사

Inventor： 김재필 ,  고동환

IPC: H01L21/28

Abstract: PURPOSE: A method for fabricating a metal interconnection of a semiconductor device is provided to prevent a defect in a metal layer caused by developer or an etch member during a fabricating process by forming a lower passivation layer, and to easily guarantee a step coverage of the metal layer by continuously performing a high temperature reflow process. CONSTITUTION: An insulation layer is formed on a substrate(10). A predetermined portion of the insulation layer is etched to form a contact hole exposing the surface of the substrate. Titanium and nitride titanium are continuously deposited on the insulation layer, the sidewall of the contact hole and the substrate exposed to the inside of the contact hole to form the first barrier layer(18). Aluminium is deposited on the barrier layer and in the contact hole to form a metal layer(20). The metal layer is reflowed so that the metal layer is filled in the contact hole. The lower passivation layer(22) is formed on the reflowed metal layer, including an oxide material for preventing the metal layer from being damaged during a subsequent process. Nitride titanium is deposited on the lower passivation layer to form the second barrier layer(24).

Abstract translation: 目的：提供一种用于制造半导体器件的金属互连的方法，以通过形成下钝化层来防止在制造过程中由显影剂或蚀刻部件引起的金属层的缺陷，并且容易地保证 通过连续进行高温回流处理而形成金属层。 构成：在基板（10）上形成绝缘层。 蚀刻绝缘层的预定部分以形成暴露衬底表面的接触孔。 钛和氮化钛连续地沉积在绝缘层上，接触孔的侧壁和暴露于接触孔内部的衬底以形成第一阻挡层（18）。 铝在阻挡层和接触孔中沉积以形成金属层（20）。 金属层被回流，使得金属层填充在接触孔中。 下部钝化层（22）形成在回流金属层上，包括用于防止金属层在随后的过程中被损坏的氧化物材料。 氮化钛被沉积在下钝化层上以形成第二阻挡层（24）。

公开(公告)号：KR100308204B1

公开(公告)日：2001-11-01

申请号：KR1019990033139

申请日：1999-08-12

Applicant: 삼성전자주식회사

Inventor： 심광보 ,  고동환 ,  서정근 ,  이영우

IPC: H01L21/28

Abstract: 본발명은반도체제조방법중 소자간의콘택형성방법에관한것으로, 비트라인을형성할때, 상기비트라인사이에콘택패드를동시에형성한다. 그리고나서, 상기콘택패드상부에콘택플러그를형성하므로오정렬마진을줄일수 있다. 또한, 상기콘택패드와비트라인간의충분한격리마진을확보할수 있으며상기콘택플러그와콘택패드간의접촉면적을확보할수 있어서콘택저항을줄일수 있는효과가있다.

公开(公告)号：KR1020010055526A

公开(公告)日：2001-07-04

申请号：KR1019990056742

申请日：1999-12-10

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  김남중 ,  김홍일 ,  고동환

IPC: H01L27/115

Abstract: PURPOSE: A method for etching gate of non-volatile memory device is provided to prevent an inferiority due to a residue of electric conduction layer a degradation of a device by, preventing generation of fitting on a surface of a substrate while realizing a vertical profile of a gate, and minimizing the loss of a field oxide layer. CONSTITUTION: A field oxide layer(101) is formed on a semiconductor substrate(100) to separate the semiconductor substrate(100) into to an active area and a field area. A tunnel oxide layer(102), a floating gate layer(104), interlayer dielectric layer(106), a control gate layer(110), and a capping layer(112) are sequentially formed on the substrate(100). A photoresist film pattern(114) is formed on the top of the capping layer(112). The photoresist film pattern(114) is used as a mask to etch the capping layer(112). The photoresist film pattern(114) is used as the mask to sequentially etch the control gate layer(110), the interlayer dielectric layer(106) and the floating gate layer(104). The floating gate layer(104) is etched in an oxygen-system gas atmosphere.

Abstract translation: 目的：提供一种用于蚀刻非易失性存储器件的栅极的方法，以防止由于导电层残留导致器件劣化的劣化，从而防止在衬底的表面上产生拟合，同时实现垂直形状 栅极，并使场氧化物层的损耗最小化。 构成：在半导体基板（100）上形成场氧化物层（101），以将半导体衬底（100）分离成有源区域和场区域。 在衬底（100）上依次形成隧道氧化物层（102），浮栅层（104），层间电介质层（106），控制栅极层（110）和覆盖层（112）。 在覆盖层（112）的顶部上形成光致抗蚀剂膜图案（114）。 光致抗蚀剂膜图案（114）用作掩模以蚀刻封盖层（112）。 光致抗蚀剂膜图案（114）用作掩模以顺序蚀刻控制栅极层（110），层间介电层（106）和浮栅层（104）。 在氧系气体气氛中蚀刻浮栅层（104）。