메모리 시스템, 메모리 테스트 시스템 및 이의 테스트 방법
    1.
    发明公开
    메모리 시스템, 메모리 테스트 시스템 및 이의 테스트 방법 有权
    存储器系统,存储器测试系统及其方法

    公开(公告)号:KR1020100088897A

    公开(公告)日:2010-08-11

    申请号:KR1020090008038

    申请日:2009-02-02

    CPC classification number: G11C29/56 G11C29/56012 G11C2029/5602 Y10T29/49004

    Abstract: PURPOSE: A memory system, a memory test system, and a testing method thereof are provided to maintain the quality of a clock signal by optically splitting the clock signal. CONSTITUTION: A memory test system comprises a system memory(MEM1,MEM2), a tester(120), and an optical splitting module(140). The tester generates a clock signal and a test signal for testing the memory. The optical splitting module includes an electro-optic signal converter(142), an optical signal splitter(144), and an optic-electro signal converter(146). The electro-optic signal converter outputs an optical clock signal and an optical test signal by converting the clock signal and the test signal into an optical signal. The optical signal splitter splits the optical test signal and the optical test signal into n signals. The optic-electric signal converter converts the split optical clock signal and test signal into the electric signal used in the memory.

    Abstract translation: 目的:提供存储器系统,存储器测试系统及其测试方法,以通过光学分离时钟信号来保持时钟信号的质量。 构成:存储器测试系统包括系统存储器(MEM1,MEM2),测试器(120)和光分离模块(140)。 测试仪产生时钟信号和测试信号,用于测试存储器。 光分路模块包括电光信号转换器(142),光信号分离器(144)和光电信号转换器(146)。 电光信号转换器通过将时钟信号和测试信号转换为光信号来输出光时钟信号和光测试信号。 光信号分路器将光学测试信号和光学测试信号分为n个信号。 光电信号转换器将分裂光时钟信号和测试信号转换为存储器中使用的电信号。

    SOI 웨이퍼를 사용한 캡 웨이퍼 제조방법, 제조된 캡웨이퍼를 사용한 반도체 칩 제조방법 및 제조된 반도체 칩
    3.
    发明授权
    SOI 웨이퍼를 사용한 캡 웨이퍼 제조방법, 제조된 캡웨이퍼를 사용한 반도체 칩 제조방법 및 제조된 반도체 칩 失效
    SOI应用程序,用户指南,附录,附录,附录,附录,附录,说明书,附录,附图及附图中的详细说明

    公开(公告)号:KR100643769B1

    公开(公告)日:2006-11-10

    申请号:KR1020050064138

    申请日:2005-07-15

    Abstract: A cap wafer manufacturing method, a semiconductor chip manufacturing method using a cap wafer and a semiconductor chip thereby are provided to simplify manufacturing processes and to reduce fabrication costs by acquiring easily through holes using an SOI wafer. An SOI wafer comprises an upper silicon layer(210), an insulating layer(220) and a lower silicon layer(230). A plurality of through holes(240) are formed on the resultant structure by etching selectively the upper silicon layer. The plurality of through holes are used for exposing the insulating layer to the outside. A plating process is performed on the through holes. The thickness of the upper silicon layer is in a predetermined range of 40 to 50 mum.

    Abstract translation: 提供帽晶片制造方法,使用帽晶片和半导体芯片的半导体芯片制造方法,以通过使用SOI晶片容易获得通孔来简化制造工艺并降低制造成本。 SOI晶片包括上硅层(210),绝缘层(220)和下硅层(230)。 通过选择性地蚀刻上硅层而在所得结构上形成多个通孔(240)。 多个通孔用于将绝缘层暴露于外部。 在通孔上执行电镀工艺。 上硅层的厚度在40至50μm的预定范围内。

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