公开(公告)号：KR1020090009638A

公开(公告)日：2009-01-23

申请号：KR1020070073092

申请日：2007-07-20

Applicant: 삼성전자주식회사

Inventor： 박찬진 ,  김정우 ,  채수두 ,  한정희 ,  그리센코 ,  나이스로브

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28282 ,  H01L27/11565 ,  H01L27/11568

Abstract: A nonvolatile memory element is provided to reduce an electric field by using a second blocking insulation film and reduce trap charge density by using a first blocking insulation film, thereby lengthening a retention time of a device and reducing back tunneling currents during an erase operation. A nonvolatile memory element comprises a tunnel insulating layer formed on a semiconductor substrate, a charge trapping layer formed on the tunnel insulating layer, a blocking insulation film formed on the charge trapping layer, and a control gate electrode formed on the blocking insulation film. The blocking insulation film more includes a first blocking insulation film and a second blocking insulation film. At this time, the bulk trap density of the first blocking insulation film is smaller than the bulk trap density of the second blocking insulation film. The first blocking insulation film is arranged between the charge trapping layer and the second blocking insulation film. The second blocking insulation film uses a high dielectric insulating layer in which a dielectric rate is larger than the tunnel insulating layer. The thickness of the first blocking insulation film is 1 nm to 100 nm. The thickness of the second blocking insulation film is 1 to 100 nm.

Abstract translation: 提供了一种非易失性存储元件，通过使用第二阻挡绝缘膜来减少电场，并通过使用第一阻挡绝缘膜来减小陷阱电荷密度，从而延长器件的保持时间并减少擦除操作期间的隧穿电流。 非易失性存储元件包括形成在半导体衬底上的隧道绝缘层，形成在隧道绝缘层上的电荷俘获层，形成在电荷俘获层上的阻挡绝缘膜，以及形成在阻挡绝缘膜上的控制栅电极。 阻挡绝缘膜更包括第一阻挡绝缘膜和第二阻挡绝缘膜。 此时，第一阻挡绝缘膜的体积陷阱密度小于第二阻挡绝缘膜的体积陷阱密度。 第一阻挡绝缘膜布置在电荷俘获层和第二阻挡绝缘膜之间。 第二阻挡绝缘膜使用电介质率大于隧道绝缘层的高介电绝缘层。 第一阻挡绝缘膜的厚度为1nm〜100nm。 第二阻挡绝缘膜的厚度为1〜100nm。