Abstract:
본 발명은 플래시 메모리 장치를 제공한다. 상기 장치는 제 1 도전형을 갖는 반도체 기판으로부터 돌출되어 일 방향으로 연장되는 반도체 핀, 상기 반도체 핀의 상부(upper portion) 및 상기 반도체 핀의 하부(lower portion)에 각각 제공되어 서로 수직으로 이격된 제 2 도전형의 제 1 도핑층 및 제 2 도핑층, 및 상기 일 방향과 교차하도록 상기 반도체 핀의 표면 상으로 연장하는 복수의 워드 라인들을 포함한다. 상기 반도체 핀과 상기 워드 라인들 사이에 터널 절연막, 전하저장막 및 블로킹 절연막이 개재한다. 상기 복수개의 워드 라인들은 상기 제 1 도핑층 및 상기 제 2 도핑층과 중첩되어, 상기 플래시 메모리 장치를 수직 채널을 갖도록 한다. 수직 채널, 반도체 핀, 플래시, 집적도, 셀프 부스팅
Abstract:
PURPOSE: An apparatus and a method for handover optimization in a broadband wireless communication system are provided to adjust the timing of handover by judging the wrong handover and the occurrence of an RLF(Radio Link Failure) in a broadband wireless communication system. CONSTITUTION: A method for handover optimization in a broadband wireless communication system comprises the steps of: judging whether or not one of plural time intervals exceeds a critical time due to handover(301-305); deciding whether to move up or delay the timing of handover depending on the time interval which exceeds the critical time(306); changing a handover parameter to move up or delay the timing of handover(315); and using the history of the handover to judge whether or not an RLF(Radio Link Failure) results from the delay or the moving-up of the timing of the handover(317).
Abstract:
PURPOSE: A method for optimizing an ANR configuration in a mobile communication system for efficiently using Inter-RAT/frequency cells in a base station is provided to optimize an ANR(Automatic Neighbor Relation) by adding, deleting and ranking the NR in the Inter-RAT/frequency cells. CONSTITUTION: A base station determines an adjacent cell reported from a terminal to an ON(Overlay Neighbor). The signal qualification of a serving cell(310) is bigger than a first reference value. The adjacent cell reported from a terminal is determined as an HN(Horizontal Neighbor). The signal qualification of the serving cell is smaller than a second reference value. The second reference value is set as the value smaller than the first reference value.
Abstract translation:目的:提供一种用于优化移动通信系统中ANR配置的方法,用于有效地使用基站中的RAT间/频率小区,以通过在Inter-RAT /频率小区中添加,删除和排列NR来优化ANR(自动邻居关系) RAT /频率单元。 构成:基站确定从终端向ON(覆盖邻居)报告的相邻小区。 服务小区(310)的信号限定大于第一参考值。 从终端报告的相邻小区被确定为HN(水平邻居)。 服务小区的信号限定小于第二参考值。 将第二参考值设置为小于第一参考值的值。
Abstract:
PURPOSE: A 3D memory device is provided so that the manufacturing cost can be reduced in comparison with the other 3D memory device formed into the multilayer. CONSTITUTION: A 3D memory device comprises the semiconductor substrate(100), the insulating layer(150) between the plane word line(160) and the gate, activity post(180), and information storage film(170) is included. The semiconductor substrate comprises the common source area. The insulating layer is by turns laminated between plane word lines and gate on the semiconductor substrate.
Abstract:
PURPOSE: An apparatus and a method for transmitting emergency call in wireless cellular communication system, capable of increasing detection rate of help signal offer the efficient emergency call transmission strategy of a terminal capable of synchronous acquisition with the reception of the synchronous channel. In that way the transmission performance of the help signal is enhanced. CONSTITUTION: A BS(base station) reserves a help signal for a predetermined number of preamble for help signal of terminals of the coverage outside a reservation(401). The base station implements a signal reception with the other nodes with the rest preamble except a preamble(403). It looks at within the coverage of the base station from the specific terminal the presence of the help signal generation terminal and the base station receives a message(405). The base station assigns the amble for the urgency call service relay to the specific terminal(407).
Abstract:
A non-volatile memory transistor including an active pillar having a sloped sidewall, a non-volatile memory array having the same, and a method for fabricating the same are provided to reduce power consumption by improving program efficiency. An active pillar(P) is protruded from a semiconductor substrate(10). The active pillar includes a sloped sidewall formed continuously from a surface of the semiconductor substrate. A gate electrode is formed to surround the sloped sidewall of the active pillar. An electric charge storage layer(23) is inserted between the active pillar and the gate electrode. A drain region(10d) is formed in an inside of an upper region of the active pillar. A source region(10s) is formed in the inside of the semiconductor substrate adjacent to a lower region of the active pillar.
Abstract:
A non-volatile memory device and a manufacturing method thereof are provided to increase integration degree of a substrate by reducing a diameter or a width of a semiconductor pillar. A first doping layer(115) of a first conductive type is formed on a substrate(105). A semiconductor pillar(120) of a second conductive type is formed on the first doping layer. The second conductive type is opposite to the first conductive type. A control gate electrode(150a) is formed to surround a sidewall of the semiconductor pillar. An electric charge storage layer(140a) is inserted between the semiconductor pillar and the control gate electrode. A second doping layer(130) of the first conductive type is arranged on the second semiconductor pillar in order to be electrically connected to the semiconductor pillar.
Abstract:
An NVM(non-volatile memory) device is provided to improve electron injection efficiency by making the injection direction of electrons passing through the bottom surface of a charge trap layer have the transfer direction of electrons. A semiconductor substrate(104) includes a bottom part(104c) and a vertical part vertically protruding from the bottom part. The vertical part includes first and second vertical parts(104a,104b). A first vertical part is positioned in the upper part of the semiconductor substrate with respect to a boundary step. The second vertical part is positioned under the first vertical part, greater in width than the first vertical part and protruding to the outside of the first vertical part. A charge trap layer(134) is positioned outside the first vertical part and on the boundary step. A control gate electrode(150) is positioned on the bottom part and outside the second vertical part and the charge trap layer. A first insulation layer(124) can be interposed between the semiconductor substrate and the charge trap layer. A second insulation layer(144) can be interposed between the semiconductor substrate and the control gate electrode.
Abstract:
다치형 비휘발성 기억 장치를 제공한다. 이 비휘발성 기억 장치는 소오스 영역 및 드레인 영역 사이에 정의된 채널 영역과, 상기 채널 영역 상부에 위치하고 전하가 저장되는 전하저장층과, 상기 채널 영역 및 상기 전하저장층 사이에 개재되어 전하가 터널링되는 터널절연막을 구비한다. 터널절연막에는 양자 제한 효과를 나타내는 양자 제한막을 포함함으로써 기입 전압에 따라 터널링 전류가 계단형으로 증가하여 데이터 비트 사이의 문턱 전압 간격이 크고, 문턱 전압의 산포가 낮은 특성을 나타낸다. 멀티비트, 다치형, 비휘발성, 소노스