公开(公告)号：KR1020080069761A

公开(公告)日：2008-07-29

申请号：KR1020070007378

申请日：2007-01-24

Applicant: 삼성전자주식회사

Inventor： 이고은 ,  이공수 ,  김경석 ,  김비오 ,  노주희 ,  형용우 ,  한재종

IPC: H01L21/336

Abstract: A method for forming a semiconductor device is provided to form temperatures of nitride layer patterns in two stages in order to fill gaps without void and to restrict pitting induction when forming a gate electrode. Upper parts of a second silicon nitride layer, a first silicon nitride layer, and a second silicon layer are removed by a chemical and mechanical polishing process or an etch back process to expose an upper surface of a first nitride layer pattern(110) and to form a second silicon layer pattern(122), a first silicon nitride layer pattern(124), and a second silicon nitride layer pattern(126) in a first opening. The first silicon nitride layer pattern and the second silicon nitride layer pattern have a third nitride layer pattern(125). The first nitride layer pattern, the third nitride layer pattern, and the second silicon layer pattern are agitated on a first silicon layer(106). A second pas oxide layer(104) is formed on the substrate. First silicon layer patterns are formed on an active region and a field region(102) of the cell region.

Abstract translation: 提供一种用于形成半导体器件的方法，以在两个阶段中形成氮化物层图案的温度，以便填充无空隙的间隙，并且在形成栅电极时限制点蚀感应。 通过化学和机械抛光工艺或回蚀工艺去除第二氮化硅层，第一氮化硅层和第二硅层的上部部分以暴露第一氮化物层图案（110）的上表面，并且 在第一开口中形成第二硅层图案（122），第一氮化硅层图案（124）和第二氮化硅层图案（126）。 第一氮化硅层图案和第二氮化硅层图案具有第三氮化物层图案（125）。 第一氮化物层图案，第三氮化物层图案和第二硅层图案在第一硅层（106）上被搅拌。 在衬底上形成第二氧化层（104）。 第一硅层图案形成在单元区域的有源区和场区（102）上。

公开(公告)号：KR1020090008650A

公开(公告)日：2009-01-22

申请号：KR1020070071756

申请日：2007-07-18

Applicant: 삼성전자주식회사

Inventor： 노주희 ,  김경석 ,  이창훈 ,  김비오 ,  형용우 ,  한재종

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4916 ,  H01L21/266 ,  H01L21/28211 ,  H01L21/823842

Abstract: A method for forming a thin film structure and a method for forming a gate electrode using the same are provided to reduce a process failure of a patterning process by preventing the particle from remaining on the surface of the thin film structure due to an organic material. A first thin film(102) is formed on a substrate(100). A part of the first thin film is doped with the impurity. A thermal process using the oxygen gas is performed in the first thin film doped with the impurity. The organic material remaining the first thin film is removed. An oxide film(106) is formed on the first thin film. A second thin film on the oxide film is made of the nitride.

Abstract translation: 提供了一种用于形成薄膜结构的方法和使用其形成栅电极的方法，以通过防止由于有机材料而使颗粒残留在薄膜结构的表面上而减少图案化过程的处理失败。 第一薄膜（102）形成在基板（100）上。 第一薄膜的一部分掺杂有杂质。 在掺杂有杂质的第一薄膜中进行使用氧气的热处理。 去除剩下第一薄膜的有机材料。 在第一薄膜上形成氧化膜（106）。 氧化膜上的第二薄膜由氮化物制成。

公开(公告)号：KR1020080060424A

公开(公告)日：2008-07-02

申请号：KR1020060134465

申请日：2006-12-27

Applicant: 삼성전자주식회사

Inventor： 김경석 ,  이공수 ,  김비오 ,  이고은 ,  노주희

IPC: H01L21/336

Abstract: A method for forming a semiconductor device is provided to restrict void within a conductive layer when filling up the recesses and openings with the conductive layer by forming the upper portion of the recess whose width is same or smaller than the openings. A silicon layer and a nitride layer pattern having a first aperture exposing the silicon layer are formed on a substrate having a reclaimed oxide pattern. A silicon pattern having a second aperture(124) exposing the substrate is formed by etching the silicon layer using the nitride pattern as an etch mask. A third aperture is formed by performing the isotropic etching to the silicon pattern. A recess(130) is formed within the reclaimed oxide pattern by performing anisotropic etching. The recess is expanded by etching a part of the exposed oxide pattern. A gate insulation layer(134) is formed by performing oxidation to the substrate, a side surface of the silicon pattern, and an inner side of the recess. A gate conductor layer filling up the recess is formed.

Abstract translation: 提供一种形成半导体器件的方法，通过形成宽度等于或小于开口的凹部的上部，在通过导电层填充凹部和开口时，限制导电层内的空隙。 在具有再生氧化物图案的基板上形成具有暴露硅层的第一孔的硅层和氮化物层图案。 通过使用氮化物图案作为蚀刻掩模蚀刻硅层，形成具有暴露衬底的第二孔径（124）的硅图案。 通过对硅图案进行各向同性蚀刻来形成第三孔。 通过进行各向异性蚀刻在再生氧化物图案内形成凹部（130）。 通过蚀刻暴露的氧化物图案的一部分来扩展凹部。 通过对基板进行氧化，硅图案的侧表面和凹部的内侧形成栅极绝缘层（134）。 形成填充凹部的栅极导体层。