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公开(公告)号：KR1019930003619B1
公开(公告)日：1993-05-08
申请号：KR1019890020106
申请日：1989-12-29
Applicant: 삼성전자주식회사
Abstract: The pulse width and the pulse interval of motor driving signal are adjusted by using a program stored in an EEPROM. The analog watch includes a memory (100) having a data to select one clock pulse among clock pulses of different pulse widths and intervals, a sense amplifier (200) for reading selection data stored in the memory (100), a latch (300) for storing output signal of the sense amplifier (200) and for tansmitting data transmitted from external input unit to the memory (100), a decoder (400) for selecting clock pulse according to output signal of the latch (300), and a motor driver (600) for generating motor drive signal according to output signal of the decoder (400).
Abstract translation: 通过使用存储在EEPROM中的程序来调整电机驱动信号的脉冲宽度和脉冲间隔。 模拟手表包括具有在不同脉冲宽度和间隔的时钟脉冲之间选择一个时钟脉冲的数据的存储器（100），用于读取存储在存储器（100）中的选择数据的读出放大器（200），锁存器（300） 用于存储读出放大器（200）的输出信号并用于将从外部输入单元发送的数据转换到存储器（100）的解码器（400），用于根据锁存器（300）的输出信号选择时钟脉冲;以及电机 驱动器（600），用于根据解码器（400）的输出信号产生电动机驱动信号。
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公开(公告)号：KR1019900006165B1
公开(公告)日：1990-08-24
申请号：KR1019870013611
申请日：1987-11-30
Applicant: 삼성전자주식회사
IPC: G11C29/00
Abstract: The circuit for operating the special mode circuit by outer signal and applying the outer voltage to the special mode circuit comprises first, second and third bias supplying taps (300-500), a reference voltage maintaining circuit (20), a voltage reducing circuit (10) dropping the input voltage, a voltage tap (300), a constant current circuit (40), and a buffer (50). The voltage reducing circuit comprises a number of transistors connected with diodes. The reference voltage maintaining circuit supplies the second bias voltage reduced to a certain level to a control node (60).
Abstract translation: 用于通过外部信号操作特殊模式电路并将外部电压施加到特殊模式电路的电路包括第一，第二和第三偏压供应抽头（300-500），参考电压保持电路（20），降压电路 10）降低输入电压，电压抽头（300），恒流电路（40）和缓冲器（50）。 电压降低电路包括与二极管连接的多个晶体管。 参考电压维持电路将减小到一定电平的第二偏置电压提供给控制节点（60）。
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公开(公告)号：KR1019890001847B1
公开(公告)日：1989-05-25
申请号：KR1019860003537
申请日：1986-05-07
Applicant: 삼성전자주식회사
IPC: H01L27/00
CPC classification number: G11C29/785
Abstract: The circuit replaces the normal line connected to a defective normal memory cell with redundant line connected to normal memory cell on a selected address signal. The circuit includes a normal decoder, an address signal generator for selecting normal memory cell connected to normal line and a redundant decoder having 1 address signal added program.
Abstract translation: 该电路用连接到所选择的地址信号上的正常存储器单元的冗余线路连接到有缺陷的普通存储器单元的法线。 该电路包括正常解码器，用于选择连接到法线的正常存储器单元的地址信号发生器和具有1个地址信号相加程序的冗余解码器。
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Patent Agency Ranking
公开(公告)号：KR1019910006241B1
公开(公告)日：1991-08-17
申请号：KR1019880016648
申请日：1988-12-14
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/31701
Abstract: The multiple test mode selection circuit in a semiconductor device is capable of extending the number of option modes by using a general address/control pad. The circuit comprises first to fifth address/control pads (5-9) for receiving an input voltage upon a read/write operation, first to fifth buffers (10-14) for buffering the inputted signal through the pads (5-9) to connect to an internal circuit of a chip, a slave decoder (20) and a master decoder (25) each coupled to a number of buffers (10-14) to select a sub mode or a main mode, a mode selector (30) for selecting a specific mode, and a high voltage sensing circuit (15) for control an operation of the selector (30).
Abstract translation: 半导体器件中的多重测试模式选择电路能够通过使用通用地址/控制板来扩展选项模式的数量。 电路包括用于在读/写操作时接收输入电压的第一至第五地址/控制焊盘（5-9），用于通过焊盘（5-9）缓冲输入信号的第一至第五缓冲器（10-14）至 连接到芯片的内部电路，从属解码器（20）和主解码器（25），每个耦合到多个缓冲器（10-14）以选择子模式或主模式，模式选择器（30） 以及用于控制选择器（30）的操作的高压感测电路（15）。
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公开(公告)号：KR1019940004404B1
公开(公告)日：1994-05-25
申请号：KR1019900019568
申请日：1990-11-30
Applicant: 삼성전자주식회사
IPC: G11C16/02
Abstract: The device for reducing the chip size replaces the function of the memory cell for writing the security call code to a dummy cell row (42) of a memory cell array (40) as well as removing one out of two I/O registers. The function of the removed register is replaced by a page buffer (38). A first security call code latched by the page buffer is read byte by byte with an I/O register (32). It is compared to a second security call code input through an I/O buffer (30). If both of them is equal, the first one is written to a dummy cell row (42). If not, an error signal is provided.
Abstract translation: 用于减小芯片尺寸的装置将存储单元的功能替换为将安全呼叫代码写入存储单元阵列（40）的虚拟单元行（42），以及从两个I / O寄存器中移除一个。 删除的寄存器的功能被页面缓冲区（38）替换。 由页缓冲器锁存的第一个安全通话代码用I / O寄存器（32）逐字节读取。 将其与通过I / O缓冲器（30）输入的第二安全呼叫代码进行比较。 如果它们都相等，则将第一个写入虚拟单元行（42）。 如果没有，则提供错误信号。
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公开(公告)号：KR1019930010942B1
公开(公告)日：1993-11-17
申请号：KR1019910014125
申请日：1991-08-16
Applicant: 삼성전자주식회사
IPC: H03K19/00
CPC classification number: G06F7/026
Abstract: Series comparator compares the data of multi-inputted series values with the data of interal circuit to decide a command execution. The series comparator of low address bit (LAB) includes a latch circuit (40) which latches two NOR gates (13),(14), the output of NOR gate (11) being inputted to the series comparator. The latched value is inverted by an inverter (IN5). The series comparator for maximal address bit (MAB) includes a latch circuit (70) which latches NOR gates (23),(24), the output of NOR gate (19) being inputted to the series comparator. The latched value is inverted by an inverter (IN9). Even when the data of input and the No of data varies, this comparator has the stable series action.
Abstract translation: 串联比较器将多输入串联值的数据与内部电路的数据进行比较，以决定执行命令。 低地址位（LAB）的串行比较器包括锁存两个或非门（13），（14）的锁存电路（40），或非门（11）的输出被输入到串联比较器。 锁存值由逆变器（IN5）反相。 用于最大地址位（MAB）的串行比较器包括锁存电路（70），其锁存NOR门（23），（24），NOR门（19）的输出被输入到串联比较器。 锁存值由逆变器（IN9）反相。 即使输入数据和数据数量不同，该比较器也具有稳定的串联动作。
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