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公开(公告)号：KR1019890001847B1
公开(公告)日：1989-05-25
申请号：KR1019860003537
申请日：1986-05-07
Applicant: 삼성전자주식회사
IPC: H01L27/00
CPC classification number: G11C29/785
Abstract: The circuit replaces the normal line connected to a defective normal memory cell with redundant line connected to normal memory cell on a selected address signal. The circuit includes a normal decoder, an address signal generator for selecting normal memory cell connected to normal line and a redundant decoder having 1 address signal added program.
Abstract translation: 该电路用连接到所选择的地址信号上的正常存储器单元的冗余线路连接到有缺陷的普通存储器单元的法线。 该电路包括正常解码器，用于选择连接到法线的正常存储器单元的地址信号发生器和具有1个地址信号相加程序的冗余解码器。
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