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公开(公告)号：WO2023027380A1
公开(公告)日：2023-03-02
申请号：PCT/KR2022/011737
申请日：2022-08-08
Applicant: 삼성전자주식회사
Abstract: 로봇이 개시된다. 로봇은 카메라, 구동부 및 프로세서를 포함할 수 있다. 프로세서는 카메라를 통해 촬영된 영상에서 하나의 그룹에 포함되는 복수의 사용자가 식별되면 복수의 사용자 각각의 프로필 정보를 획득하고, 획득된 프로필 정보에 기초하여 그룹의 그룹 타입 정보, 복수의 사용자의 우선 순위 정보 및 그룹의 선호 경유지 정보를 포함하는 그룹 특징 정보를 획득하고, 획득된 그룹 특징 정보 및 목적지 정보에 기초하여 경로 안내 기능을 수행하도록 구동부를 제어할 수 있다.
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公开(公告)号：KR1020070056670A
公开(公告)日：2007-06-04
申请号：KR1020050115641
申请日：2005-11-30
Applicant: 삼성전자주식회사
CPC classification number: H01L24/02 , H01L2924/01082
Abstract: A bonding pad for inspecting a semiconductor wafer is provided to secure a stable bonding region by forming a predetermined pattern on an electrical inspection region thereof. A probe tip comes in contact with an electrical inspection region(118) in order to perform an electrical characteristic inspection for a semiconductor device. An external lead line is electrically connected to a bonding region(116). The electrical inspection region has a predetermined pattern(119). The predetermined pattern has a concave structure, a convex structure or a concavo-convex structure. A planar shape of the predetermined pattern is a circle shape or a polygonal shape.
Abstract translation: 提供用于检查半导体晶片的接合焊盘，以通过在其电气检查区域上形成预定图案来确保稳定的接合区域。 探针尖端与电气检查区域（118）接触，以便对半导体器件进行电气特性检查。 外部引线与接合区域（116）电连接。 电检查区域具有预定图案（119）。 预定图案具有凹形结构，凸形结构或凹凸结构。 预定图案的平面形状是圆形或多边形。
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公开(公告)号：KR100630685B1
公开(公告)日：2006-10-02
申请号：KR1020040046560
申请日：2004-06-22
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: G11C29/028 , G11C29/48 , G11C29/50012 , G11C2029/2602 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014
Abstract: 다른 칩을 경유하여 입력 신호를 전달하는 집적회로 장치 및 집적회로 멀티 칩 패키지가 개시된다. 상기 집적회로 멀티칩 패키지/집적회로 장치에서는, 제1 칩의 로직 회로에 필요한 입력신호가 제2 칩의 로직 회로에도 필요한 경우에, 동기화기를 경유하여 제1 칩과 제2 칩 각각의 로직 회로들에 동시에 입력신호를 전달한다. 3개 이상의 더 많은 칩들을 하나의 패키지 내에 패키징 하는 경우에도, 동기화기를 경유한 해당 입력신호를 다른 칩들에도 선택적으로 전달할 수 있다.
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公开(公告)号：KR1020040041750A
公开(公告)日：2004-05-20
申请号：KR1020020069613
申请日：2002-11-11
Applicant: 삼성전자주식회사
IPC: G11C7/00
Abstract: PURPOSE: A bank voltage control device using block selection information of a semiconductor memory device and its control method are provided to prevent an overshoot of a bank voltage by supplying a corresponding voltage according to the position of an array block in a bank. CONSTITUTION: According to the method for controlling a bank voltage using memory block selection information, array block selection signals(Block0-Block15) arranged remotely from a bank voltage driver are detected using an active memory array block selection signal. And the second bank voltage is supplied to a memory bank(100) by driving a normal size driver and an over-size driver when the array block selection signal is detected.
Abstract translation: 目的：提供使用半导体存储器件的块选择信息的库电压控制装置及其控制方法，以通过根据阵列中的阵列块的位置提供相应的电压来防止堤电压的过冲。 构成：根据使用存储块选择信息来控制存储体电压的方法，使用有源存储器阵列块选择信号检测远离存储体电压驱动器布置的阵列块选择信号（Block0-Block15）。 并且当检测到阵列块选择信号时，通过驱动正常大小的驱动器和超大尺寸的驱动器将第二存储体电压提供给存储体（100）。
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公开(公告)号：KR1020040000911A
公开(公告)日：2004-01-07
申请号：KR1020020035925
申请日：2002-06-26
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/06 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/48472 , H01L2224/4912 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , Y10T29/49121 , H01L2224/45099 , H01L2924/00
Abstract: PURPOSE: A method for arranging pads to prevent a bonding error and a signal skew is provided to prevent the short circuit of a bonding wire by arranging pads in an inverse V-shaped line or a V-shaped line. CONSTITUTION: The second pad is located at a predetermined position apart from the first pad. The second pad is located at an upper end of a right side. The third pad is located at a predetermined position apart from the second pad. The third pad is located at the upper end of the right side. The fourth pad is located at a predetermined position apart from the third pad. The fourth pad is located at a lower end of the right side. The fifth pad is located at a predetermined position apart from the fourth pad. The fifth pad is located at the lower end of the right side. The first to the fifth pad are formed with POC(Pad On Cell) type pads.
Abstract translation: 目的：提供一种用于布置衬垫以防止接合误差和信号偏斜的方法，以通过将衬垫布置在V形线或V形线中来防止接合线短路。 构成：第二垫位于与第一垫隔开的预定位置处。 第二垫位于右侧的上端。 第三垫位于与第二垫隔开的预定位置处。 第三垫位于右侧的上端。 第四垫位于与第三垫隔开的预定位置处。 第四垫位于右侧的下端。 第五垫位于与第四垫隔开的预定位置处。 第五个垫位于右侧的下端。 第一至第五焊盘由POC（Pad On Cell）型焊盘形成。
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Patent Agency Ranking
公开(公告)号：KR1020030064959A
公开(公告)日：2003-08-06
申请号：KR1020020005053
申请日：2002-01-29
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method of forming interconnection in a semiconductor device is provided to prevent a leakage current without forming a leakage current preventing layer. CONSTITUTION: A groove for interconnection is formed in an interlayer dielectric(50). An element(for example, N2) for preventing a leakage current is doped on the interlayer dielectric. A material for interconnection is stacked and the groove is filled.
Abstract translation: 目的：提供一种在半导体器件中形成互连的方法，以防止泄漏电流而不形成防漏电流层。 构成：在层间电介质（50）中形成用于互连的沟槽。 用于防止漏电流的元件（例如，N2）被掺杂在层间电介质上。 用于互连的材料被堆叠并且凹槽被填充。
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公开(公告)号：KR1020030056803A
公开(公告)日：2003-07-04
申请号：KR1020010087104
申请日：2001-12-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a damascene metal line of a semiconductor device is provided to be capable of restraining the increase of leakage current by completely removing remaining metal using a dry etching process. CONSTITUTION: After sequentially forming the first insulating layer(410) and the first metal layer pattern(420) on a semiconductor substrate(400), the second insulating layer(430) is formed on the first metal layer pattern. A plurality of contact holes are formed by selectively etching the second insulating layer for exposing the first metal layer pattern. The second metal layer pattern(445) is formed in the contact hole. At this time, metal residues are formed on the second insulating layer. The upper portion of the second insulating layer is removed by carrying out a dry etching process using the etching selectivity between the second insulating layer and the second metal layer pattern for protruding the upper portion of the second metal layer pattern. At this time, the metal residues are completely removed. Then, the third insulating layer is formed on the entire surface of the resultant structure.
Abstract translation: 目的：提供一种用于形成半导体器件的镶嵌金属线的方法，其能够通过使用干蚀刻工艺完全除去剩余的金属来限制漏电流的增加。 构成：在半导体衬底（400）上依次形成第一绝缘层（410）和第一金属层图案（420）之后，第二绝缘层（430）形成在第一金属层图案上。 通过选择性蚀刻用于暴露第一金属层图案的第二绝缘层形成多个接触孔。 第二金属层图案（445）形成在接触孔中。 此时，金属残留物形成在第二绝缘层上。 通过使用第二绝缘层和第二金属层图案之间的蚀刻选择性进行干蚀刻工艺来去除第二绝缘层的上部，以突出第二金属层图案的上部。 此时，金属残留物被完全除去。 然后，在所得结构的整个表面上形成第三绝缘层。
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公开(公告)号：KR1020000013323A
公开(公告)日：2000-03-06
申请号：KR1019980032133
申请日：1998-08-07
Applicant: 삼성전자주식회사
IPC: H01L21/768
Abstract: PURPOSE: A multiple wiring structure in a semiconductor device is provided to reduce a parasitic capacitance generated between an upper wiring and a lower wiring by eliminating an interlayer dielectric between the wiring. CONSTITUTION: The multiple wiring structure comprises: a lower wiring formed on the semiconductor substrate; a contact plug formed on the lower wiring; an upper wiring electrically connected to the lower wiring by the contact plug; and a plurality of pillars for supporting the upper wiring from the lower wiring and the semiconductor substrate.
Abstract translation: 目的：提供半导体器件中的多重布线结构，通过消除布线之间的层间电介质来减少上布线和下布线之间产生的寄生电容。 构成：多重配线结构包括：在半导体衬底上形成的下布线; 形成在下布线上的接触塞; 通过接触插头电连接到下布线的上布线; 以及用于从下布线和半导体基板支撑上布线的多个支柱。
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公开(公告)号：KR1020060133741A
公开(公告)日：2006-12-27
申请号：KR1020050053554
申请日：2005-06-21
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: H01L2924/0002 , H01L2924/00
Abstract: A semiconductor memory chip having displaying units discriminating a probe test region from a wire bonding region is provided to reduce the number of defect semiconductor memory chips by easily distinguishing the probe test region and the wire bonding region. A semiconductor memory chip(300) has plural pads(NP1-NPn). Each of the pads has a probe test region(320) and a wire bonding region(330) connected to a test probe. The semiconductor memory chip has display units(A1-An) discriminates the probe test region from the wire bonding region between the pads. The displaying unit is located in the middle of the probe test region and the wire bonding region. The semiconductor memory chip has plural pad units including one or more pads. The displaying unit is formed between the respective pad units. The displaying unit is made of metal and polyimide.
Abstract translation: 提供具有从引线接合区域区分探针测试区域的显示单元的半导体存储器芯片，以通过容易地区分探针测试区域和引线接合区域来减少缺陷半导体存储器芯片的数量。 半导体存储芯片（300）具有多个焊盘（NP1-NPn）。 每个焊盘具有连接到测试探针的探针测试区域（320）和引线接合区域（330）。 半导体存储器芯片具有显示单元（A1-An），用于区分探针测试区域与焊盘之间的引线接合区域。 显示单元位于探头测试区域和引线接合区域的中间。 半导体存储器芯片具有包括一个或多个焊盘的多个焊盘单元。 显示单元形成在各个垫单元之间。 显示单元由金属和聚酰亚胺制成。
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公开(公告)号：KR1020050115107A
公开(公告)日：2005-12-07
申请号：KR1020040040397
申请日：2004-06-03
Applicant: 삼성전자주식회사
IPC: H01L23/12 , H01L25/065
CPC classification number: H01L25/074 , H01L23/49816 , H01L24/04 , H01L24/12 , H01L24/44
Abstract: 적층식 반도체 패키지를 제공한다. 이 패키지는 제1 돌출 단자들에 의해 기초 인쇄 회로 보드에 직접 접촉하는 제1 칩과, 제2 돌출 단자들에 의해 커버 인쇄 회로 보드에 직접 접촉하는 제2 칩을 포함한다. 커버 인쇄 회로 보드는 칩들을 덮으며, 기초 인쇄 회로 보드에 연결되어 있다. 이로써, 본딩 와이어들의 수를 감소시킬 수 있다.
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