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公开(公告)号：KR1020140112241A
公开(公告)日：2014-09-23
申请号：KR1020130026725
申请日：2013-03-13
Applicant: 삼성전자주식회사
CPC classification number: H03L7/10 , H03L7/095 , H03L7/0997 , H03L2207/50
Abstract: A method for operating all-digital phase-locked loop (ADPLL) comprises a step of comparing a reference clock signal with a feedback signal of the ADPLL and outputting a comparison signal according to the comparison result, and a step of detecting whether the ADPLL is locked by using a toggling number of the comparison signal.
Abstract translation: 一种用于操作全数字锁相环（ADPLL）的方法包括将参考时钟信号与ADPLL的反馈信号进行比较并根据比较结果输出比较信号的步骤，以及检测ADPLL是否为 通过使用切换数字的比较信号锁定。
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公开(公告)号：KR101870249B1
公开(公告)日：2018-06-22
申请号：KR1020120007129
申请日：2012-01-25
Applicant: 삼성전자주식회사
CPC classification number: H03B19/00 , H03L7/00 , H03L7/099 , H03L7/16 , H03L2207/50
Abstract: 디더제어회로는분주된클락신호에응답하여의사난수시퀀스를생성하는의사난수생성기와, 상기의사난수시퀀스의적어도하나의출력비트를이용하여입력디지털코드를디더링하고상기디더된디지털코드를출력하는디더회로를포함한다. 상기디더회로는상기적어도하나의출력비트에기초하여상기입력디지털코드와상기입력디지털코드의합 또는차에대응하는디지털코드를상기디더된디지털코드로서출력할수 있다. 상기디더된디지털코드는상기분주된클락신호에따라동작하는누산기로입력될수 있다.
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公开(公告)号：KR1020140090455A
公开(公告)日：2014-07-17
申请号：KR1020130002535
申请日：2013-01-09
Applicant: 삼성전자주식회사
CPC classification number: H03L7/093 , H03L7/0895
Abstract: The present invention relates to a phase locked loop circuit. The phase locked loop circuit according to the present invention includes a bang bang phase frequency detector which receives a reference signal and a feedback signal, detects a phase difference between the reference signal and the feedback signal, and outputs a detection signal; an analog to digital mixed filter which receives the detection signal and outputs a control signal based on the received detection signal; a voltage controlled oscillator which outputs an output signal in response to the control signal; and a divider which outputs a feedback signal by dividing the output signal by 1/n.
Abstract translation: 本发明涉及一种锁相环电路。 根据本发明的锁相环电路包括接收参考信号和反馈信号的爆轰相位频率检测器，检测参考信号和反馈信号之间的相位差，并输出检测信号; 模拟数字混合滤波器，其接收检测信号并基于接收到的检测信号输出控制信号; 压控振荡器，其响应于所述控制信号输出输出信号; 以及通过将输出信号除以1 / n来输出反馈信号的分频器。
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公开(公告)号：KR1020130086405A
公开(公告)日：2013-08-02
申请号：KR1020120007129
申请日：2012-01-25
Applicant: 삼성전자주식회사
CPC classification number: H03B19/00 , H03L7/00 , H03L7/099 , H03L7/16 , H03L2207/50
Abstract: PURPOSE: A dither control circuit and devices having the same are provided to facilitate a clock signal generation device that increase a frequency resolution of a digitally controlled oscillator (DCO) by using an output signal of an accumulator. CONSTITUTION: A dither control circuit (20A) includes a pseudo random number generator (21) and a dither circuit (22A). The pseudo random number generator includes a linear feedback shift register (LFSR) that generates a pseudo random number sequence in response to a frequency-divided clock signal; and a bit inversion control circuit that inverts and outputs at least one output bit per period of the LFSR. The dither circuit dithers an input digital code by using the at least one output bit of the pseudo random number sequence and outputs a dithered digital code. The dither circuit outputs a digital code corresponding to a sum of or a difference between the input digital code and the input digital code as the dithered digital code based on the at least one output bit.
Abstract translation: 目的：提供抖动控制电路及其装置，以便于通过使用累加器的输出信号来增加数字控制振荡器（DCO）的频率分辨率的时钟信号发生装置。 构成：抖动控制电路（20A）包括伪随机数发生器（21）和抖动电路（22A）。 伪随机数发生器包括响应于分频时钟信号产生伪随机数序列的线性反馈移位寄存器（LFSR）; 以及位反转控制电路，其反转并输出每个LFSR的每个周期的至少一个输出位。 抖动电路通过使用伪随机数序列的至少一个输出位来抖动输入数字码，并输出抖动数字码。 抖动电路基于至少一个输出位，输出对应于输入数字码和输入数字码之和的差分的数字码作为抖动数字码。
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Patent Agency Ranking
公开(公告)号：KR1020140132539A
公开(公告)日：2014-11-18
申请号：KR1020130051824
申请日：2013-05-08
Applicant: 삼성전자주식회사
CPC classification number: H03L7/0991 , H03K5/133 , H03K5/135 , H03L7/0995 , H03L2207/50
Abstract: A digital control oscillator includes: the odd number of first inverters which are connected in a ring-shape; and multiple inverter stages which include the odd number of second inverters, respectively. Each of the odd number of the second inverters included in each of the multiple inverter stages is connected to each of the odd number of the first inverters in a row. The odd number of the second inverters included in a part of the multiple inverter stages is enabled or disabled at the same time by a row unit. Each of the odd number of the second inverters included in the remaining inverter stages of the multiple inverter stages is enabled or disabled independently.
Abstract translation: 数字控制振荡器包括：以环形连接的奇数个第一反相器; 以及分别包括奇数个第二反相器的多个反相器级。 包含在多个逆变器级的每一个中的奇数个第二反相器中的每一个连续地连接到奇数个第一反相器中的每一个。 多个逆变器级的一部分中包括的奇数个第二反相器通过行单元同时被使能或禁止。 多个反相器级的剩余反相器级中包括的奇数个第二反相器中的每一个独立地被使能或禁止。
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9.发明公开
公开(公告)号：KR1020140113216A
公开(公告)日：2014-09-24
申请号：KR1020130028321
申请日：2013-03-15
Applicant: 삼성전자주식회사
CPC classification number: H03L7/085 , H03L7/0995 , H03L7/113 , H03L7/18 , H03L7/193 , H03L7/1976 , H03L2207/50
Abstract: Disclosed are a digital phase-locked loop (DPLL) circuit using a phase-to-digital converter, a method for operating the same, and an apparatus comprising the same. The DPLL comprises a digital control oscillator changing a frequency and a phase of an output oscillation signal in response to a digital control code; a main frequency divider dividing a frequency of the output oscillation signal to generate a first feedback signal; and a phase-to-digital converter dividing the phase of the output oscillation signal and generating a quantization code acquired by converting the phase difference between a reference signal and the first feedback signal into a digital value by using the divided phase signal, wherein the digital control code is generated based on the quantized code.
Abstract translation: 公开了使用相对数字转换器的数字锁相环（DPLL）电路，其操作方法以及包括该数字锁相环的装置。 DPLL包括响应于数字控制码改变输出振荡信号的频率和相位的数字控制振荡器; 主分频器，分频输出振荡信号的频率，产生第一反馈信号; 以及相位数字转换器，其分频输出振荡信号的相位，并通过使用分频相位信号产生通过将参考信号和第一反馈信号之间的相位差转换为数字值而获得的量化代码，其中数字 基于量化代码产生控制代码。
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公开(公告)号：KR1020140113006A
公开(公告)日：2014-09-24
申请号：KR1020130027808
申请日：2013-03-15
Applicant: 삼성전자주식회사
IPC: G05F1/10
Abstract: A current generator according to an embodiment of the present invention includes a first current generation circuit which generates a first current including a first current noise according to the change of a supply voltage, a second current generation circuit which generates a second current including a second current noise according to the change of the supply voltage, and a current reduction circuit which generates a third current which excludes the first current noise and the second current noise by reducing the second current from the first current. An electronic system according to the embodiment of the present invention, a stable operation can be performed by generating a current regardless of the change of a supply voltage.
Abstract translation: 根据本发明的实施例的电流发生器包括：第一电流产生电路，其根据电源电压的变化产生包括第一电流噪声的第一电流;第二电流产生电路，其生成包括第二电流的第二电流 根据电源电压的变化产生噪声，以及电流降低电路，其通过从第一电流减少第二电流产生排除第一电流噪声和第二电流噪声的第三电流。 根据本发明实施例的电子系统，无论电源电压的变化如何，都可以通过产生电流来执行稳定的操作。
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