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公开(公告)号：KR101552939B1
公开(公告)日：2015-09-15
申请号：KR1020090028536
申请日：2009-04-02
Applicant: 삼성전자주식회사
CPC classification number: G11C29/36 , G11C29/1201 , G11C2029/3602
Abstract: 메모리셀의테스트를위한반도체장치및 테스트방법이개시된다. 상기반도체장치는데이터가인가되는복수의단자들, 대응하는단자에서출력하는데이터를수신하여대응하는메모리셀로출력하는복수의버퍼들및 상기복수의버퍼들을제어하는복수의제어신호들을발생하여출력하는제어부를구비할수 있고, 상기각각의버퍼는상기복수의단자들에동일한데이터를인가하여대응하는메모리셀의불량을테스트하는테스트모드에서, 대응하는제어신호에응답하여상기수신된데이터의논리상태를변경하거나변경함이없이출력할수 있다.
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公开(公告)号：KR1020140031515A
公开(公告)日：2014-03-13
申请号：KR1020120097252
申请日：2012-09-03
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/1016 , G06F2212/7208
Abstract: Provided is a memory controller capable of controlling a plurality of planes of a nonvolatile memory device to perform an operating command at the same time. The memory controller comprises: a host interface configured to receive, from a host, a first operating command and a plurality of plane logic information of a memory device; a microprocessor configured to decode the first operating command into a second operating command and map the plane logic information to the memory device; a register configured to queue the second operating command and the mapped plane logic information; a memory interface configured to provide the second operating command and the queued plane logic information to the memory device; and a plane control unit configured to control a plurality of planes corresponding to the mapped plane logic information to perform the second operating command at the same time in the memory device.
Abstract translation: 提供了一种能够控制非易失性存储装置的多个平面以同时执行操作命令的存储器控制器。 存储器控制器包括：主机接口，被配置为从主机接收第一操作命令和存储器设备的多个平面逻辑信息; 配置成将第一操作命令解码为第二操作命令并将平面逻辑信息映射到存储器装置的微处理器; 配置为对所述第二操作命令和所映射的平面逻辑信息进行排队的寄存器; 存储器接口，被配置为向存储器设备提供第二操作命令和排队的平面逻辑信息; 以及平面控制单元，被配置为控制与所映射的平面逻辑信息相对应的多个平面，以在所述存储器件中同时执行所述第二操作命令。
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公开(公告)号：KR1020100110122A
公开(公告)日：2010-10-12
申请号：KR1020090028536
申请日：2009-04-02
Applicant: 삼성전자주식회사
CPC classification number: G11C29/36 , G11C29/1201 , G11C2029/3602
Abstract: PURPOSE: A semiconductor device for testing a memory cell and a testing method thereof are provided to rapidly test the memory cell by detecting a short between data transmission lines. CONSTITUTION: Terminals(DQ0, DQ4, DQ8, DQ12) are connected to a channel. A plurality of buffers(BUF_0,BUF_4,BUF_8,BUF_12) receive data outputted from the corresponding terminal and output the received data to the memory cell. The output signal of the buffer is applied to the corresponding memory cell through latch units(LATCH_0,LATCH_4,LATCH_8,LATCH_12). The latch unit latches on to the output signal of the corresponding buffer and outputs the latched signal. A controller(250) generates first to fourth control signals and outputs the generated control signals to the buffer.
Abstract translation: 目的：提供一种用于测试存储单元的半导体器件及其测试方法，用于通过检测数据传输线之间的短路来快速测试存储器单元。 构成：端子（DQ0，DQ4，DQ8，DQ12）连接到通道。 多个缓冲器（BUF_0，BUF_4，BUF_8，BUF_12）接收从相应终端输出的数据并将接收的数据输出到存储单元。 缓冲器的输出信号通过锁存单元（LATCH_0，LATCH_4，LATCH_8，LATCH_12）施加到相应的存储单元。 锁存单元锁存相应缓冲器的输出信号，并输出锁存信号。 控制器（250）产生第一至第四控制信号，并将产生的控制信号输出到缓冲器。
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公开(公告)号：KR1020100108699A
公开(公告)日：2010-10-08
申请号：KR1020090026835
申请日：2009-03-30
Applicant: 삼성전자주식회사
IPC: G11C11/4093 , G11C11/4096 , G11C11/4074
CPC classification number: G11C7/1078 , G11C7/1084
Abstract: PURPOSE: The input buffer circuit of a semiconductor device including a regulating function for an input level is provided to optimize the input level of an input signal applied to an input buffer using a mode-register set-signal and a fuse option. CONSTITUTION: An input buffer(22) responds a selected bias voltage(SBBp) in order to regulate the input level of an input signal(IN). A voltage generator(10) and a voltage distributor(11) generate and distribute the bias voltage into bias voltages with different levels. Selectors(20, 21) select one of the bias voltages with different levels according to a selection signal. The selectors apply the selected bias voltage to the input buffer.
Abstract translation: 目的：提供包括输入电平调节功能的半导体器件的输入缓冲电路，以使用模式寄存器设置信号和保险丝选项来优化施加到输入缓冲器的输入信号的输入电平。 构成：为了调节输入信号（IN）的输入电平，输入缓冲器（22）响应选定的偏置电压（SBBp）。 电压发生器（10）和电压分配器（11）产生并将偏置电压分配到具有不同电平的偏置电压。 选择器（20,21）根据选择信号选择不同电平的偏置电压之一。 选择器将选定的偏置电压施加到输入缓冲器。
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Patent Agency Ranking
公开(公告)号：KR1020090010777A
公开(公告)日：2009-01-30
申请号：KR1020070074150
申请日：2007-07-24
Applicant: 삼성전자주식회사
CPC classification number: G11C5/146 , G05F1/465 , G11C7/20 , G11C2207/2227
Abstract: A cell plate voltage generator and a semiconductor memory device including the same are provided to improve operation reliability by supplying a cell plate voltage of enough voltage level. A memory cell array(60) comprises a plurality of memory cells. Each memory cell comprises one capacitor(C) and one transistor(Q). An internal power voltage generation part(20) generates an internal power voltage(IVC) according to an external power voltage(EVC). An external initialization signal generation part(40) generates a generating enable signal according to the external power voltage. The generating enable signal is an initialization signal(VCCHB-EVC) based on the external power voltage. A first sub cell plate voltage generation part(30) generates a first cell plate voltage(Vcp-1) according to the internal power voltage. A second sub cell plate voltage generation part(50) receives the external power voltage in response to the initialization signal based on the external power voltage, and generates a second cell plate voltage(Vcp-2) according to the external power voltage.
Abstract translation: 提供一种单元板电压发生器和包括该单元板电压发生器的半导体存储器件，以通过提供具有足够电压电平的单元板电压来提高操作可靠性。 存储单元阵列（60）包括多个存储单元。 每个存储单元包括一个电容器（C）和一个晶体管（Q）。 内部电源电压产生部件（20）根据外部电源电压（EVC）产生内部电源电压（IVC）。 外部初始化信号生成部（40）根据外部电源电压生成发生使能信号。 产生使能信号是基于外部电源电压的初始化信号（VCCHB-EVC）。 第一子电池板电压产生部件（30）根据内部电源电压产生第一电池板电压（Vcp-1）。 第二子单元板电压产生部件（50）根据外部电源电压响应于初始化信号接收外部电源电压，并根据外部电源电压产生第二单元电池电压（Vcp-2）。
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公开(公告)号：KR1020080067039A
公开(公告)日：2008-07-18
申请号：KR1020070004087
申请日：2007-01-15
Applicant: 삼성전자주식회사
IPC: H03K19/0175
CPC classification number: H03K19/018521 , H03K3/356113 , H03K19/0013
Abstract: A level shifter circuit for low power consumption is provided to prevent a leakage current by cutting off a current path generated in a DPD(Deep Power Down) mode. A level shifter circuit for low power consumption includes a pull-up unit(110), a pull-down unit(120), and a cutting-off unit(130). The pull-up unit pulls up an input voltage signal and outputs the pulled-up input voltage signal to an output node. The pull-down unit pulls down the input voltage signal and outputs the pulled-down input voltage to the output node. The cutting-off unit controls the connection of the pull-up unit and the pull-down unit in a specific mode. The level shifter circuit further includes a latch unit for preventing the floating of the output node in the specific node.
Abstract translation: 提供了用于低功耗的电平移位器电路，以通过切断在DPD（深度掉电）模式中产生的电流路径来防止泄漏电流。 一种用于低功耗的电平移位器电路包括上拉单元（110），下拉单元（120）和切断单元（130）。 上拉单元拉出输入电压信号，并将上拉输入电压信号输出到输出节点。 下拉单元拉下输入电压信号，并将下拉输入电压输出到输出节点。 切断单元以特定模式控制上拉单元和下拉单元的连接。 电平移位器电路还包括用于防止输出节点在特定节点中漂浮的锁存单元。
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公开(公告)号：KR1020170046389A
公开(公告)日：2017-05-02
申请号：KR1020150146666
申请日：2015-10-21
Applicant: 삼성전자주식회사
CPC classification number: H03K5/1565 , H03L7/0891
Abstract: 듀티사이클정정회로, 이를포함하는반도체장치및 듀티사이클정정회로의동작방법이개시된다. 본발명의기술적사상에따른듀티사이클정정회로는, 입력신호의듀티를조절하여출력하는듀티정정부와, 차지펌핑동작및 카운팅동작에기반하여상기듀티조절에관련된정정코드를발생하는듀티검출부및 제1 클록에동기하여상기차지펌핑동작에관련된제1 제어신호및 상기카운팅동작에관련된제2 제어신호를생성하는타이밍제어부를구비하는것을특징으로한다.
Abstract translation: 公开了占空比校正电路，包括该占空比校正电路的半导体器件以及操作占空比校正电路的方法。 根据本发明的技术特征，是根据占空比校正单元上的占空比校正电路，和一个电荷泵浦操作和用于输出用来控制输入信号占空比检测单元的占空比，用于生成与所述占空比控制和校正码的计数操作 以及定时控制单元，用于与一个时钟同步地产生与电荷泵浦操作有关的第一控制信号和与计数操作有关的第二控制信号。
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公开(公告)号：KR1020140030733A
公开(公告)日：2014-03-12
申请号：KR1020120097254
申请日：2012-09-03
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: Provided is a memory controller capable of receiving a plurality of addresses of a nonvolatile memory device and controlling a plurality of planes of the nonvolatile memory device to perform an operating command at the same time. The memory controller comprises: a first interface configured to receive, from a host, a first command, a first address corresponding to the first command, a second address, an address state separation command separating the first and second addresses, and a second command corresponding to the second address; and a microprocessor configured to control to decode the first command, map the first address, and perform the decoded first command in a nonvolatile memory device using the first address in which the decoded first command is mapped, and to determine the correlation between the first and second addresses with reference to the address state separation command, wherein the correlation determines whether the first and second commands are respectively performed in the first and second addresses at the same time.
Abstract translation: 提供了一种能够接收非易失性存储装置的多个地址并且控制非易失性存储装置的多个平面以同时执行操作命令的存储器控制器。 存储器控制器包括：第一接口，被配置为从主机接收第一命令，对应于第一命令的第一地址，第二地址，分离第一和第二地址的地址状态分离命令，以及对应于第二命令的第二命令 到第二个地址; 以及微处理器，被配置为控制对第一命令进行解码，映射第一地址，并使用其中解码的第一命令映射的第一地址在非易失性存储器件中执行解码的第一命令，并且确定第一和第 参考地址状态分离命令的第二地址，其中相关性确定在第一和第二地址中是否同时执行第一和第二命令。
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