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公开(公告)号：KR100092367B1
公开(公告)日：1995-12-02
申请号：KR1019920021455
申请日：1992-11-14
Applicant: 삼성전자주식회사
Inventor： 박용보
IPC: G11C11/407
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公开(公告)号：KR100080845B1
公开(公告)日：1994-12-28
申请号：KR1019910014272
申请日：1991-08-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
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公开(公告)号：KR1019940008286B1
公开(公告)日：1994-09-09
申请号：KR1019910014272
申请日：1991-08-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
CPC classification number: G11C5/147 , G05F1/465 , G06F1/28 , G06F2201/81 , G11C11/4074 , G11C29/50
Abstract: The power circuit providing internal power in the semiconductor memory has voltage detector (100) sensing the external applied voltage level; a driver controller (200) activating or deactivating a comparator means (300); a driver (50) generating the internal voltage level according to the control signal from the driver controller (200). The power circuit makes the final testing-and-verification steps easy because the circuit can produce the internal voltage which is the same as the applied voltage level.
Abstract translation: 在半导体存储器中提供内部功率的电源电路具有检测外部施加的电压电平的电压检测器（100）; 驱动器控制器（200）激活或去激活比较器装置（300）; 根据来自驾驶员控制器（200）的控制信号产生内部电压电平的驱动器（50）。 电源电路使得最终的测试和验证步骤变得容易，因为电路可以产生与施加的电压电平相同的内部电压。
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公开(公告)号：KR1019940006081B1
公开(公告)日：1994-07-06
申请号：KR1019910019739
申请日：1991-11-07
Applicant: 삼성전자주식회사
IPC: G11C11/40
Abstract: The device consists of a decoder which decodes given incoming addresses, a driver which puts a output signal from the decoder into an input node, and amplifies that signal to drive memory cell, a wordline driver which is inserted between a driver and a decoder and consists of discharge elements to discharge a voltage applied to the input nodes of the driver when the memory cell is unselected, and a capacitor which is inserted between the input nodes of the driver and a ground to restrain the voltage going up when the memory cell is unselected.
Abstract translation: 该装置包括解码给定输入地址的解码器，将解码器的输出信号放入输入节点的驱动器，并放大该信号以驱动存储器单元;插入在驱动器和解码器之间的字线驱动器， 的放电元件，以在不选择存储器单元时放电施加到驱动器的输入节点的电压;以及电容器，其插入在驱动器的输入节点和地之间，以在不选择存储器单元时抑制电压上升 。
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Patent Agency Ranking
公开(公告)号：KR1019930007653B1
公开(公告)日：1993-08-14
申请号：KR1019910012635
申请日：1991-07-23
Applicant: 삼성전자주식회사
IPC: H03M7/00
Abstract: According to the highly integrated semiconductor memory device, the number of decoder circuit proportionally increases memory cells. To speed up the chip action, the output of decoder operates rapidly. Block select signal has the effect of loading, decreasingly. Its result brings the speed-up of word line signal outputs. Memory decoder circuits divide among them memory cell arrays which have individual blocks in each column. Each of the decoder circuits is composed of 2nd pull-up transistors. Pull-up transistors are P-MOS transistors. Pull-down transistors are N-MOS transistors. And 1st pull-up transistor is smaller than 2nd pull-up transistor. It is possible for decoder circuit to speed-up operation.
Abstract translation: 根据高度集成的半导体存储器件，解码器电路的数量按比例地增加存储器单元。 为了加快芯片动作，解码器的输出速度很快。 块选择信号具有加载，减少的效果。 其结果带来了字线信号输出的加速。 存储器解码器电路在它们之间划分在每列中具有各个块的存储单元阵列。 每个解码器电路由第二上拉晶体管组成。 上拉晶体管是P-MOS晶体管。 下拉式晶体管是N-MOS晶体管。 而第一个上拉晶体管小于第二个上拉晶体管。 解码器电路可以加速运行。
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公开(公告)号：KR1019930003001B1
公开(公告)日：1993-04-16
申请号：KR1019900010972
申请日：1990-07-19
Applicant: 삼성전자주식회사
IPC: H03K3/00
CPC classification number: G11C5/063 , G11C7/1051
Abstract: The CMOS driver circuit for data output buffer comprises a pull-up PMOS transistor (PM) having a first current electrode connected to a power voltage (Vcc), a second current electrode connected to an output node and a control electrode receiving the input signals, a pull-down NMOS transistor (NM) having a first current electrode connected to a ground voltage, a second current electrode connected to the output node and a control electrode receiving inverted input signals, nd a limiter (D) connected between the supply voltage (Vcc) and the first current electrode of the pull-up PMOS transistor (PM) to reduce the PMOS transistor engaging level to a value determining the output node (N3) and reduce its peak current to a preset level if the output state change is rising, thereby reducing the output interference.
Abstract translation: 用于数据输出缓冲器的CMOS驱动器电路包括具有连接到电源电压（Vcc）的第一电流电极，连接到输出节点的第二电流电极和接收输入信号的控制电极的上拉PMOS晶体管（PM） 具有连接到接地电压的第一电流电极的下拉式NMOS晶体管（NM），连接到输出节点的第二电流电极和接收反相输入信号的控制电极，以及连接在电源电压 Vcc）和上拉PMOS晶体管（PM）的第一电流电极，以将PMOS晶体管接合电平降低到确定输出节点（N3）的值，并且如果输出状态变化上升，则将其峰值电流降低到预设电平 ，从而减少输出干扰。
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公开(公告)号：KR100128042B1
公开(公告)日：1998-04-21
申请号：KR1019930024243
申请日：1993-11-15
Applicant: 삼성전자주식회사
Inventor： 박용보
IPC: G11C29/00
Abstract: 본 발명은 반도체집적회로에서 특히 메모리쎌 어레이내의 특정 단일비트가 결함으로 발생할 시에 이를 단일 결함비트 단위로 구제가 이루지도록 하는 반도체집적회로에 관한 것으로 본 발명은 반도체집적회로가 리던던시동작의 유무에 대응하여 결함구제를 위한 데이타를 직접으로 출력하는 단일비트 구제회로를 구비하는 기술에 관하여 개시하고 있다. 이로부터 단일비트 단위로 결함구제가 이루어지는 반도체집적회로를 제공함에 의해. 리던던시의 효율 및 고속의 액세스를 크게 증가시킬 수 있다. 또한 비트단위로 결함구제가 이루어짐에 의해 리던던트용 쎌들이 점유하는 면적으로 최소로 할 수 있는 효과도 있다.
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