Abstract:
A display driving circuit comprises a source driver and a timing controller. The source driver drives source lines of a display panel. The timing controller transmits image data to the source driver and controls the source driver for the transmitted image data to be displayed through the display panel. The timing controller randomizes the image data in a scrambling mode based on the state of the image data when data packets including pixel data having the image data written are transmitted to the source driver.
Abstract:
PURPOSE: A method for transmitting data through a shared back channel, a multifunctional driver circuit for transmitting data, and a display driving device using the same are provided to implement proper control by receiving inner data generated in an inner circuit and the test data of a panel without additional lines. CONSTITUTION: A driver(25) is controlled by a controller(220). The driver comprises an input terminal(IN). The driver is connected to a common bus(CB). The driver has a first operation mode or a second operation mode.
Abstract:
PURPOSE: A mode converting method, a display driving IC applying the same, and an image signal processing system are provided to minimize power consumed in a display driving system by a power down mode for constant time. CONSTITUTION: A display driving IC includes a timing control device(110) and a plurality of source driving devices(120n). At least one of the timing device and source driving devices operates at a power down mode in one section of an initializing section, a data transmission section, and a vertical blank section.
Abstract:
DDI등의장치에서적합한데이터전송방법이개시되어있다. 그러한데이터전송방법에서, 제1 동작모드에서는공유백 채널을통해소프트페일신호가전송될수 있다. 또한, 상기제1 동작모드와는다른제2 동작모드에서는상기공유백 채널을통해리드아웃데이터가전송될수 있다. 본발명의실시예에따르면, 리드아웃데이터가공유백 채널을통해전송됨에의해내부또는외부에서테스트또는그에따른적절한제어가효과적으로수행된다.
Abstract:
PURPOSE: A method for transmitting display data is provided to reduce power consumption by operating a source driver by composition data according to a channel property of the source driver. CONSTITUTION: A clock training signal is received from a timing controller(S310). A test pattern is received from the timing controller(S320). A reception level of a receiver included in a source driver is selectively controlled by a test based on the received test pattern(S330). Data with configuration data corresponding to image frame lines is received from the timing controller(S340). A modulation clock signal is received from the timing controller for a vertical blank period(S350). [Reference numerals] (AA) Start; (BB) End; (S310) Receive a clock training signal; (S320) Receive a test pattern; (S330) Control a reception level of a receiver by performing a test based on the test pattern; (S340) Receive data with configuration data in the controlled reception level; (S350) Receive a modulation clock signal
Abstract:
PURPOSE: A clock recovery circuit and a sampling signal generating device including the same are provided to use an adaptively generated clock window signal, thereby transmitting a signal at high speed. CONSTITUTION: A clock code detecting unit(110) receives a transmission signal with a clock code to detect an edge of the clock code. The clock code detecting unit generates a clock transition signal based on an edge of the clock code. A clock signal generating unit(130) generates a restoration clock signal in response to the clock transition signal.