公开(公告)号：KR1020030095781A

公开(公告)日：2003-12-24

申请号：KR1020020033352

申请日：2002-06-14

Applicant: 삼성전자주식회사

Inventor： 서길선 ,  신경선 ,  김환석

IPC: H01L21/66

Abstract: PURPOSE: A wafer map of an electrical inspection process for displaying the inspection result of plural processes is provided to be capable of checking and analyzing the results of a plurality of electrical inspection processes by using one wafer map alone. CONSTITUTION: A wafer map of an electrical inspection process is provided with a wafer map(100) for displaying the electrical inspection results of the whole wafer and a unit chip inspection state(102) for displaying the inspection result of each unit chip. At this time, the wafer map has the same shape as the wafer. Preferably, the unit chip inspection state is used for displaying the unit chip inspection result of plural processes by using a plurality of colors, numbers and combination of signs. Preferably, the plural processes includes a wafer state electrical inspection process and a package state electrical inspection process.

Abstract translation: 目的：提供用于显示多个处理的检查结果的电气检查处理的晶片图，以便能够通过单独使用一个晶片图来检查和分析多个电气检查处理的结果。 构成：对电气检查过程的晶片图提供有用于显示整个晶片的电检查结果的晶片图（100）和用于显示每个单元芯片的检查结果的单元芯片检查状态（102）。 此时，晶片图具有与晶片相同的形状。 优选地，单元芯片检查状态用于通过使用多种颜色，数字和符号的组合来显示多个处理的单元芯片检查结果。 优选地，多个处理包括晶片状态电检查处理和封装状态电检查处理。

公开(公告)号：KR1020080057099A

公开(公告)日：2008-06-24

申请号：KR1020060130453

申请日：2006-12-19

Applicant: 삼성전자주식회사

Inventor： 김동건 ,  강성모 ,  서길선

IPC: H01L21/66

CPC classification number: G01R31/2601 ,  G01R1/07314

Abstract: A wafer test method using a probe card is provided to minimize the number of inspections by easily supplying a one-shot inspection region and an inspection method. The entire area of a wafer is mapped to form a map(S100). The maximum value of a one-shot inspection region(para) of a probe card is set(S200). A plurality of inspection blocks which are not more than the maximum value of the one-shot inspection region are set(S300). Each inspection block sequentially and respectively inspects a partial region of the map, transferring from the outer part of the map to the inside of the map(S400). With respect to each inspection block, the number of inspections is calculated to inspect every region of the map corresponding to a region of a plurality of semiconductor chip on the wafer by a minimum number of inspections(S500). The calculated numbers of inspections are compared to calculate a minimum number of inspections(S600). A one-shot inspection region and an inspection transfer direction of the probe card are determined to correspond to the calculated minimum number of inspections(S700). A plurality of semiconductor chips formed on the wafer are inspected by using the probe card whose one-shot inspection region and inspection transfer direction are determined(S800). The para of the probe card can have one of 32, 64, 128, 256 or 512.

Abstract translation: 提供使用探针卡的晶片测试方法，以便通过容易地提供一次性检查区域和检查方法来最小化检查次数。 映射晶片的整个区域以形成映射（S100）。 设置探针卡的一次检查区域（para）的最大值（S200）。 设定不大于一次检查区域的最大值的多个检查块（S300）。 每个检查块依次地分别检查地图的部分区域，从地图的外部部分转移到地图的内部（S400）。 对于每个检查块，计算检查次数以通过最小检查次数来检查与晶片上的多个半导体芯片的区域对应的每个区域的区域（S500）。 将计算出的检查次数进行比较，以计算最少的检查次数（S600）。 确定探针卡的单次检查区域和检查传送方向，以对应于计算的最小检查次数（S700）。 通过使用确定了一次检查区域和检查传送方向的探针卡来检查形成在晶片上的多个半导体芯片（S800）。 探针卡的对位可以有32,64,128,256或512之一。

公开(公告)号：KR1020030096566A

公开(公告)日：2003-12-31

申请号：KR1020020033131

申请日：2002-06-14

Applicant: 삼성전자주식회사

Inventor： 박세호 ,  서길선 ,  김환석

IPC: H04L1/00

CPC classification number: H04L1/0061 ,  H03M13/096

Abstract: PURPOSE: A method for generating checksum bits is provided to enhance a level of error verification by improving an existing checksum method. CONSTITUTION: A method for generating checksum bits includes a calculation process(S120-S180) for calculating the sum of weight values and a checksum decision process(S200-S220) in order to check a bit error from digital data of k-numeral n-bits of bnbn-1bn-2...b2b1(k) where n and k are natural numbers and n>=1, k>=2. The calculation process(S120-S180) is to calculate the weight sum by multiplying weight values corresponding to digital data of n-bits by each other and adding the multiplied values to each other. The checksum decision process(S200-S220) is to decide the checksum by performing an M-modulus operation for the weight sum.

Abstract translation: 目的：提供一种用于产生校验和位的方法，以通过改进现有的校验和方法来提高错误验证的级别。 构成：用于产生校验和位的方法包括：计算加权值和校验和确定处理（S200-S220）之和的计算处理（S120-S180），以便从数字n- bnbn-1bn-2 ... b2b1（k）的位，其中n和k是自然数，n> = 1，k> = 2。 计算处理（S120-S180）是通过将与n位的数字数据相对应的权重值彼此相乘并将相乘的值相加来计算权重和。 校验和决定处理（S200〜S220）是通过对权重和执行M模运算来决定校验和。