公开(公告)号：KR1020030065701A

公开(公告)日：2003-08-09

申请号：KR1020020005422

申请日：2002-01-30

Applicant: 삼성전자주식회사

Inventor： 손권일 ,  조욱래 ,  이광진

IPC: G11C29/00

CPC classification number: G11C29/12015 ,  G11C29/14

Abstract: PURPOSE: A semiconductor memory device for performing a wafer test process using a high frequency is provided to check data bits received through data lines by using only one comparison circuit. CONSTITUTION: A semiconductor memory device for performing a wafer test process using a high frequency includes a memory cell array(1110), an address buffer circuit(1150), a test block signal generation portion(1160), a test clock signal generation portion(1180), a test data generation portion(1190), a test data write portion, a test data read portion, and a decision portion(1310). The memory cell array are used for storing data. The address buffer circuit is used for receiving an external address in response to a test clock signal. The test block signal generation portion generates a test block signal which is synchronized with the external clock signal in a test operation mode. The test clock signal generation portion generates a test clock signal according to the test block signal. The test data generation portion generates test data according to the test clock signal. The test data write portion writes the test data in a predetermined region of the memory cell array. The test data read portion reads the test data from the predetermined region of the memory cell array. The decision portion receives data bits and decides whether the data bits on the data lines have the same value, or not. The decision portion outputs a flag signal as a decided result.

Abstract translation: 目的：提供一种用于执行使用高频的晶片测试处理的半导体存储器件，以通过仅使用一个比较电路来检查通过数据线接收的数据位。 构成：用于使用高频执行晶片测试处理的半导体存储器件包括存储单元阵列（1110），地址缓冲电路（1150），测试块信号产生部分（1160），测试时钟信号产生部分 1180），测试数据生成部分（1190），测试数据写入部分，测试数据读取部分和判定部分（1310）。 存储单元阵列用于存储数据。 地址缓冲电路用于响应于测试时钟信号接收外部地址。 测试块信号产生部分在测试操作模式下产生与外部时钟信号同步的测试块信号。 测试时钟信号产生部分根据测试块信号产生测试时钟信号。 测试数据生成部根据测试时钟信号生成测试数据。 测试数据写入部分将测试数据写入存储单元阵列的预定区域。 测试数据读取部分从存储单元阵列的预定区域读取测试数据。 决定部分接收数据位，并确定数据线上的数据位是否具有相同的值。 决定部分输出作为判定结果的标志信号。

公开(公告)号：KR1020030085237A

公开(公告)日：2003-11-05

申请号：KR1020020023431

申请日：2002-04-29

Applicant: 삼성전자주식회사

Inventor： 김성태 ,  이광진 ,  손권일

IPC: G11C7/00

Abstract: PURPOSE: A power on reset circuit is provided, which detects the supply of an external power supply voltage(EXTVDD) accurately without regard to an increase rate of the external power supply voltage. CONSTITUTION: A differential amplifier(120) senses a voltage difference between the first input port and the second input port, and generates an output signal. The first voltage generator supplies the first voltage to the first input port of the above differential amplifier. The second voltage generator supplies the second voltage to the second input port of the differential amplifier. The first voltage generator generates the first voltage using a power supply voltage supplied from the external, and the second voltage generator generates the second voltage using an internal power supply voltage, converted from the power supply voltage supplied from the external.

Abstract translation: 目的：提供上电复位电路，可以精确检测外部电源电压（EXTVDD）的供应，而不考虑外部电源电压的增加率。 构成：差分放大器（120）感测第一输入端口和第二输入端口之间的电压差，并产生输出信号。 第一电压发生器将第一电压提供给上述差分放大器的第一输入端口。 第二电压发生器将第二电压提供给差分放大器的第二输入端口。 第一电压发生器使用从外部提供的电源电压产生第一电压，并且第二电压发生器使用从外部供应的电源电压转换的内部电源电压产生第二电压。

公开(公告)号：KR100466984B1

公开(公告)日：2005-01-24

申请号：KR1020020026906

申请日：2002-05-15

Applicant: 삼성전자주식회사

Inventor： 손권일 ,  조욱래 ,  김수철

IPC: G11C29/00

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/01327 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The chip has pads (20,21) connected to an internal circuit (19) comprising interconnected semiconductor devices to provide integrated circuit functionality. A test element group (TEG) circuit (23) measures electrical characteristics of the semiconductor devices and is connected to a TEG pad (22). A lead frame is electrically connected to the pads but not to the TEG pads. An independent claim is also included for a method of testing an integrated circuit chip.

Abstract translation: 该芯片具有连接到包括互连半导体器件的内部电路（19）的焊盘（20,21）以提供集成电路功能。 测试元件组（TEG）电路（23）测量半导体器件的电特性，并连接到TEG焊盘（22）。 引线框架电连接到焊盘但不连接到TEG焊盘。 对于测试集成电路芯片的方法也包括独立权利要求。

公开(公告)号：KR100432886B1

公开(公告)日：2004-05-22

申请号：KR1020020005422

申请日：2002-01-30

Applicant: 삼성전자주식회사

Inventor： 손권일 ,  조욱래 ,  이광진

IPC: G11C29/00

CPC classification number: G11C29/12015 ,  G11C29/14

Abstract: A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.

Abstract translation: 半导体存储器件产生具有比外部时钟信号的周期更短的周期的测试时钟信号（其周期和周期数是可变的），并且使用测试时钟信号在内部测试数据。 半导体存储器件可以在外部时钟信号的半个周期期间使用内部产生的测试时钟信号来重复执行读取/写入操作。 通过将读取操作中的输出数据与已知数据进行比较，测试装置可以确定存储器设备的存储器单元是否正常。 在低频测试装置中，可以筛选当高速存储器件以高频工作时可能发生的缺陷。

公开(公告)号：KR1020030089021A

公开(公告)日：2003-11-21

申请号：KR1020020026906

申请日：2002-05-15

Applicant: 삼성전자주식회사

Inventor： 손권일 ,  조욱래 ,  김수철

IPC: G11C29/00

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/01327 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: An integrated circuit chip including a test element group circuit and a fabrication method thereof are provided, which performs an EDS(Electric Die Sorting) test and a TEG(Test Element Group) test at the same time in each integrated circuit chip formed on a wafer without increasing test time. CONSTITUTION: The semiconductor integrated circuit device formed on a semiconductor wafer(1) includes at least one first pad(22), and a plurality of second pads connected to corresponding internal circuits respectively, and the first test element group circuit(23) connected to the first pad. The above internal circuits and the first test element group circuit are tested at the same time. The first pad is a non-bonding pad, and the second pads are bonding pads.

Abstract translation: 目的：提供一种包括测试元件组电路及其制造方法的集成电路芯片，其在形成于每个集成电路芯片的每个集成电路芯片中同时执行EDS（电动模具分选）测试和TEG（测试元件组）测试 晶片没有增加测试时间。 构成：形成在半导体晶片（1）上的半导体集成电路器件分别包括至少一个第一焊盘（22）和连接到对应的内部电路的多个第二焊盘，并且第一测试元件组电路（23）连接到 第一垫 上述内部电路和第一测试元件组电路同时进行测试。 第一焊盘是非焊盘，第二焊盘是焊盘。