公开(公告)号：KR1020040047262A

公开(公告)日：2004-06-05

申请号：KR1020020075409

申请日：2002-11-29

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: G11C11/15

CPC classification number: G11C11/161 ,  G11C5/025 ,  G11C7/18 ,  G11C8/14 ,  H01L27/228

Abstract: PURPOSE: A magnetic memory using a vertical transistor and its fabrication method are provided, which is used easily in a large integration and has a small size of a unit cell. CONSTITUTION: A plurality of pillars(130) are arranged on a semiconductor substrate(100) in two dimension and are used as a channel of a vertical transistor. A plurality of magnetic tunneling junctions(200) are arranged on an upper part of each pillar. A plurality of word lines(185) surround the pillars, and are arranged along one direction. And a plurality of bit lines(210) connect the magnetic tunneling junctions as crossing the word lines, on the magnetic tunneling junction.

Abstract translation: 目的：提供使用垂直晶体管的磁存储器及其制造方法，其容易地在大的集成中使用并且具有小尺寸的晶胞。 构成：在二维半导体衬底（100）上布置多个柱（130），并用作垂直晶体管的沟道。 在每个支柱的上部布置有多个磁性隧道结（200）。 多个字线（185）围绕支柱，沿着一个方向布置。 并且多个位线（210）在磁性隧道结上连接磁通隧道，使其与跨越字线的方向相连。

公开(公告)号：KR1020040041337A

公开(公告)日：2004-05-17

申请号：KR1020020069551

申请日：2002-11-11

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: G11C11/15

CPC classification number: G11C11/161 ,  G11C5/025 ,  G11C7/18 ,  G11C8/14 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/12

Abstract: PURPOSE: A magnetic memory having a new structure and operation method is provided, which is proper to large integration and reduces process steps. CONSTITUTION: A plurality of magnetic tunneling junctions(MTJ)(150) are arranged on a semiconductor substrate(100). A gate insulator pattern and a gate electrode are stacked on the magnetic tunneling junctions and the semiconductor substrate in sequence. And word lines are arranged on the magnetic tunneling junctions, and connect the magnetic tunneling junctions along one direction. The magnetic tunneling junction is formed with a pinning layer(142), a fixed layer(144), an insulator(146) and a free layer(148).

Abstract translation: 目的：提供一种具有新结构和操作方法的磁存储器，适用于大型集成和减少工艺步骤。 构成：在半导体衬底（100）上布置有多个磁性隧道结（MTJ）（150）。 栅极绝缘体图案和栅电极按顺序堆叠在磁隧道结和半导体衬底上。 并且字线布置在磁隧道结上，并且沿着一个方向连接磁隧道结。 磁隧道结形成有钉扎层（142），固定层（144），绝缘体（146）和自由层（148）。

公开(公告)号：KR1020040041335A

公开(公告)日：2004-05-17

申请号：KR1020020069548

申请日：2002-11-11

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: G11C11/15

CPC classification number: G11C11/161 ,  G11C5/025 ,  G11C7/18 ,  G11C8/14 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/12

Abstract: PURPOSE: A magnetic memory having a new structure and operation method is provided, which is proper to large integration and reduces process steps. CONSTITUTION: A plurality of magnetic tunneling junctions(240) are arranged on a semiconductor substrate(100) in two dimension. A plurality of bit lines(260) are arranged on the magnetic tunneling junctions, and connect the magnetic tunneling junction along one direction. And a plurality of word lines are arranged to cross the bit lines below the magnetic tunneling junctions. The word lines are used in a record operation changing information stored in the magnetic tunneling junction.

Abstract translation: 目的：提供一种具有新结构和操作方法的磁存储器，适用于大型集成和减少工艺步骤。 构成：在二维半导体衬底（100）上布置多个磁性隧道结（240）。 多个位线（260）布置在磁隧道结上，并沿着一个方向连接磁隧道结。 并且多个字线被布置成跨越磁隧道结下方的位线。 字线用于存储在磁隧道结中的记录操作改变信息。

公开(公告)号：KR1020020096808A

公开(公告)日：2002-12-31

申请号：KR1020010052394

申请日：2001-08-29

Applicant: 삼성전자주식회사

Inventor： 송승헌 ,  김우식 ,  강호규

IPC: H01L27/10

CPC classification number: G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  Y10S257/904

Abstract: PURPOSE: An STTM(Scalable Two Transistor Memory) cell array is provided to reduce easily an area of an unit cell by reducing a minimum size or a minimum design rule. CONSTITUTION: An extended data line(41) of the first column is electrically connected with a drain or a source of the first MOS transistor(Q1). The source or the drain of the first MOS transistor(Q1) is electrically connected with an external feedback line(42). An extended bit line(43) of the second column is electrically with a drain or a source of the fourth MOS transistor(Q4) and a source or a drain of the third MOS transistor(Q3). The source or the drain of the fourth MOS transistor(Q4) is electrically connected with an extended bit line(44) of the third column and the second external bit line(45). A drain or a source of the third MOS transistor(Q3) is electrically connected with an extended bit line(46) of the first column and the first external bit line(47). An extended data line(48) of the second column is electrically connected with a drain or a source of the second MOS transistor(Q2). The source or the drain of the second MOS transistor(Q2) is electrically connected with the external feedback line(42). Gates of the first and the fourth MOS transistor(Q1,Q4) are electrically with the first election line(49). Gates of the second and the third MOS transistors(Q2,Q3) are electrically connected with the second selection line(50).

Abstract translation: 目的：提供STTM（可扩展双晶体管存储器）单元阵列，通过减小最小尺寸或最小设计规则，轻松减少单位单元的面积。 构成：第一列的扩展数据线（41）与第一MOS晶体管（Q1）的漏极或源极电连接。 第一MOS晶体管（Q1）的源极或漏极与外部反馈线（42）电连接。 第二列的扩展位线（43）与第四MOS晶体管（Q4）的漏极或源极以及第三MOS晶体管（Q3）的源极或漏极电连接。 第四MOS晶体管（Q4）的源极或漏极与第三列的延伸位线（44）和第二外部位线（45）电连接。 第三MOS晶体管（Q3）的漏极或源极与第一列和第一外部位线（47）的扩展位线（46）电连接。 第二列的扩展数据线（48）与第二MOS晶体管（Q2）的漏极或源极电连接。 第二MOS晶体管（Q2）的源极或漏极与外部反馈线（42）电连接。 第一和第四MOS晶体管（Q1，Q4）的栅极与第一选择线（49）电连接。 第二和第三MOS晶体管（Q2，Q3）的栅极与第二选择线（50）电连接。

公开(公告)号：KR1020040063348A

公开(公告)日：2004-07-14

申请号：KR1020030000735

申请日：2003-01-07

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: H01L27/11

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

Abstract: PURPOSE: An SRAM(static random access memory) device composed of a vertical transistor is provided to reduce the cell size of vertical transistors, and to embody low power consumption by maintaining a sufficient size of a channel length of a transistor regardless of the cell size. CONSTITUTION: The first and second active regions of an L type are disposed in a substrate, defined by a field region. N-type and P-type doping regions are disposed in a predetermined region of the first and second active regions. Pillars are disposed on the N-type and P-type doping regions. A gate insulation layer is formed on the sidewall of the pillars to dispose the first gate electrode on the sidewall of the pillars with an access transistor. The second gate electrode is disposed on the sidewall of the pillars with a pull-up transistor and a driver transistor. The L-typed active region is interconnected with a reverse L-type active region. The pillars are interconnected by contact plugs. The first interconnection(227a) for a bitline 1, the second interconnection(227b) for a power line, the third interconnection(227c) for a ground line and the fourth interconnection(227d) for a bitline 2 are disposed in parallel with one another on the contact plugs. A wordline is disposed in the first gate electrode, perpendicular to the interconnections through a wordline contact plug.

Abstract translation: 目的：提供由垂直晶体管组成的SRAM（静态随机存取存储器）器件，以减小垂直晶体管的单元尺寸，并且通过保持晶体管的沟道长度足够大的尺寸来体现低功耗，而不考虑单元尺寸 。 构成：L型的第一和第二有源区域设置在由场区域限定的衬底中。 N型和P型掺杂区设置在第一和第二有源区的预定区域中。 支柱设置在N型和P型掺杂区域上。 在柱的侧壁上形成栅极绝缘层，以将第一栅电极设置在具有存取晶体管的柱的侧壁上。 第二栅极通过上拉晶体管和驱动晶体管设置在柱的侧壁上。 L型有源区与反向L型有源区互连。 支柱通过接触塞相互连接。 位线1的第一互连（227a），电力线的第二互连（227b），地线的第三互连（227c）和位线2的第四互连（227d）彼此并联设置 在接触塞上。 字线被布置在第一栅电极中，通过字线接触插塞垂直于互连。

公开(公告)号：KR1020030027228A

公开(公告)日：2003-04-07

申请号：KR1020010057614

申请日：2001-09-18

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: H01L29/78

Abstract: PURPOSE: A metal oxide semiconductor field effect transistor(MOSFET) with a Schottky junction is provided to solve problems like a gate depletion, a reduced transistor characteristic caused by penetration of boron and high impedance of a gate electrode by forming a gate electrode made of a metallic material. CONSTITUTION: The gate electrode(120) is disposed in a predetermined region of a semiconductor substrate(100). A gate insulation layer(110) is inserted between the gate electrode and the semiconductor substrate. A source/drain(140) is disposed in the semiconductor substrate at a side surface of the gate electrode. The gate electrode and the source/drain are made of a metallic material.

Abstract translation: 目的：提供具有肖特基结的金属氧化物半导体场效应晶体管（MOSFET），以解决诸如栅极耗尽的问题，由硼的渗透引起的降低的晶体管特性和栅电极的高阻抗，通过形成由 金属材料。 构成：栅电极（120）设置在半导体衬底（100）的预定区域中。 栅极绝缘层（110）插入在栅电极和半导体衬底之间。 源极/漏极（140）在栅电极的侧表面处设置在半导体衬底中。 栅电极和源极/漏极由金属材料制成。

公开(公告)号：KR1020030016906A

公开(公告)日：2003-03-03

申请号：KR1020010050985

申请日：2001-08-23

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: H01L21/336

Abstract: PURPOSE: A gate structure and a method for forming the same are provided to prevent the permeation of impurities into a semiconductor substrate under a gate pattern by covering the third insulating layer pattern on the first insulating layer pattern on a sidewall of a gate pattern. CONSTITUTION: A gate pattern including a gate oxide layer pattern(110), a gate conductive layer pattern(120), and a recessed polishing stop layer(131) is formed on a semiconductor substrate(100). The first insulating layer pattern(141) is arranged on a sidewall of the gate pattern. The first insulating layer pattern(141) is lower than the recessed polishing stop layer(131). The first insulating layer pattern(141) has a horizontal projection portion for covering the semiconductor substrate(100). A recessed gate spacer(152) is formed on the horizontal projection portion of the first insulating layer pattern(141). The recessed gate spacer(152) is higher than the first insulating layer pattern(141). A gap region is formed between the recessed gate spacer(152) and the recessed polishing stop layer(131). The third insulating layer pattern(161) is formed on a sidewall of the recessed gate spacer(152). An interlayer dielectric(171) is formed between the third insulating layer patterns(161). The third insulating layer pattern(162) is inserted between the recessed gate spacer(152) and the recessed polishing stop layer(131).

Abstract translation: 目的：提供一种栅极结构及其形成方法，以通过在栅极图案的侧壁上覆盖第一绝缘层图案上的第三绝缘层图案来防止杂质在栅极图案下渗透到半导体衬底中。 构成：在半导体衬底（100）上形成包括栅极氧化层图案（110），栅极导电层图案（120）和凹陷抛光停止层（131）的栅极图案。 第一绝缘层图案（141）布置在栅极图案的侧壁上。 第一绝缘层图案（141）比凹进的抛光停止层（131）低。 第一绝缘层图案（141）具有用于覆盖半导体衬底（100）的水平突出部分。 在第一绝缘层图案（141）的水平突出部分上形成有凹入的栅极间隔物（152）。 凹入的栅极间隔物（152）比第一绝缘层图案（141）高。 在凹入的间隔物（152）和凹入的抛光停止层（131）之间形成间隙区域。 第三绝缘层图案（161）形成在凹陷栅极间隔物（152）的侧壁上。 在第三绝缘层图案（161）之间形成层间电介质（171）。 第三绝缘层图案（162）插入凹入的栅极间隔物（152）和凹陷的抛光停止层（131）之间。

公开(公告)号：KR100423896B1

公开(公告)日：2004-03-22

申请号：KR1020010052394

申请日：2001-08-29

Applicant: 삼성전자주식회사

Inventor： 송승헌 ,  김우식 ,  강호규

IPC: H01L27/10

CPC classification number: G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  Y10S257/904

Abstract: A Scalable Two-Transistor Memory (STTM) cell array having a 4F unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

Abstract translation: 具有4F 2单元单元面积的可扩展双晶体管存储器（STTM）单元阵列，其中F是最小特征尺寸。 数据线和位线沿着Y轴方向交替并且彼此相邻，并且字线沿着X轴方向布置。 每个STTM单元由半导体衬底表面上的浮栅MOS感测晶体管组成，在感测晶体管顶部具有垂直双侧壁栅多隧道结势垒编程MOS晶体管。 数据线连接编程晶体管的所有源极区域，并且位线沿列方向连接感测晶体管的所有源极/漏极区域。 字线在行方向上连接编程晶体管的所有双侧壁栅极区域。 本发明还涉及一种列寻址电路以及该电路的驱动方法。

公开(公告)号：KR100391985B1

公开(公告)日：2003-07-22

申请号：KR1020010052395

申请日：2001-08-29

Applicant: 삼성전자주식회사

Inventor： 김우식 ,  송승헌 ,  강호규

IPC: H01L27/10

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

Abstract: A method of fabricating a multiple tunnel junction Scalable Two-Transistor Memory (STTM) cell array with a unit cell area as low as 4F2, F representing the minimum feature dimension, which usually is the width and also the spacing of the data lines or the write (or word or control gate) lines, wherein process sequence and conditions are designed to offer wide flexibility in material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing of memory cell devices is made compatible with peripheral CMOS devices so that the devices in both areas can be made simultaneously, thereby decreasing the total number of processing steps. Insulator filled trenches around the device regions, source/drain and the gate regions of the peripheral devices are formed simultaneously with the corresponding regions of the memory cell devices.

Abstract translation: 一种制造单元单元面积低至4F2的多隧道结可扩展双晶体管存储器（STTM）单元阵列的方法，F表示最小特征尺寸，其通常是数据线的宽度以及间距或者 写入（或字或控制栅）线，其中处理顺序和条件被设计为在STTM单元的不同区域处提供材料选择和层厚度的广泛灵活性，并且表面平面性保持在制造顺序的几个阶段。 存储器单元器件的处理与外围CMOS器件兼容，使得两个区域中的器件可以同时制造，从而减少了处理步骤的总数。 围绕器件区域，外围器件的源极/漏极和栅极区域的绝缘体填充沟槽与存储器单元器件的对应区域同时形成。

公开(公告)号：KR1020030016900A

公开(公告)日：2003-03-03

申请号：KR1020010050978

申请日：2001-08-23

Applicant: 삼성전자주식회사

Inventor： 송승헌

IPC: H01L21/265

Abstract: PURPOSE: A method for forming a PMOS transistor of a dual gate CMOS type semiconductor device is provided to prevent the diffusion of boron to a channel by maintaining the amount of boron ions implanted into a gate electrode less than the amount of boron ions implanted into a source/drain region. CONSTITUTION: A gate insulating layer is formed on a substrate(10). A polysilicon gate electrode layer is formed on the gate insulating layer. An ion implantation mask layer is formed on the gate electrode layer. A gate pattern including an ion implantation mask(151) and a gate electrode layer pattern(131) is formed by patterning the ion implantation mask layer and the gate electrode layer. Ions are implanted into a source/drain region by implanting ions including boron into the substrate including the gate pattern. The ion implantation mask(151) is removed. The ions are implanted into the gate electrode layer pattern(131).

Abstract translation: 目的：提供一种用于形成双栅极CMOS型半导体器件的PMOS晶体管的方法，以通过保持注入到栅电极中的硼离子的量小于植入到栅极电极中的硼离子的量来防止硼向沟道扩散 源/漏区。 构成：在基板（10）上形成栅极绝缘层。 在栅极绝缘层上形成多晶硅栅电极层。 在栅电极层上形成离子注入掩模层。 通过对离子注入掩模层和栅电极层进行构图，形成包括离子注入掩模（151）和栅电极层图案（131）的栅极图案。 通过将包括硼的离子注入到包括栅极图案的衬底中，将离子注入到源极/漏极区域中。 去除离子注入掩模（151）。 将离子注入到栅电极层图案（131）中。