발광 다이오드 모듈
    1.
    发明公开
    발광 다이오드 모듈 审中-实审
    发光二极管模块

    公开(公告)号:KR1020170011869A

    公开(公告)日:2017-02-02

    申请号:KR1020150105289

    申请日:2015-07-24

    CPC classification number: F21V23/005 G02F1/133603 G02F2001/133607 H01L33/58

    Abstract: 본발명의기술적사상에의한발광다이오드모듈은, 기판상에배치되는발광칩; 및상기기판상에서상기발광칩을감싸도록배치되는광학렌즈;를포함하고, 상기광학렌즈는, 상기발광칩을수납하는홈(groove)을내부에가지고, 돔형상의상면을가지는몸체부와, 상기몸체부의하면으로부터돌출되는고리형상의지지부;를포함하고, 상기광학렌즈는상기발광칩의상면및 측벽을감싸는형상일수 있다.

    Abstract translation: 提供了一种发光二极管(LED)模块。 LED模块包括:基板上的发光芯片; 以及配置为包围发光芯片的基板上的光学透镜,其中,所述光学透镜包括主体,所述主体包括在其中容纳所述发光芯片的凹槽,并且具有圆顶形的上表面和从下部突出的环形支撑部分 身体表面。

    볼 랜드부에 포켓벽을 가지는 볼 그리드 어레이 패키지들및 그의 형성 방법들
    3.
    发明公开
    볼 랜드부에 포켓벽을 가지는 볼 그리드 어레이 패키지들및 그의 형성 방법들 无效
    球窝阵列中的球栅阵列包装及其形成方法

    公开(公告)号:KR1020080058790A

    公开(公告)日:2008-06-26

    申请号:KR1020060132893

    申请日:2006-12-22

    Abstract: A ball grid array package having a pocket wall in a ball land part and a method for forming the same are provided to reduce a thickness thereof by attaching a solder ball within a predetermined region surround with the packet wall. A lead frame(10) is electrically connected to a semiconductor chip(40). The lead frame includes at least one lead(17,18), a ball land part(30) formed on the lead, and a pocket wall(33) protruded from a surface of the ball land part to surround a predetermined region. A body(50) is formed to surround the semiconductor chip and the lead frame. A solder ball(60) is arranged in the inside of the predetermined region surrounded by the pocket wall. The body is composed of an epoxy molding compound. The solder ball is composed of one of Sn-Pb-based compound, Sn-Ag-based compound, and Sn-Ag-Cu-based compound.

    Abstract translation: 提供了具有球场部分中的凹槽壁的球栅阵列封装及其形成方法,以通过将焊球安装在包壁周围的预定区域内来减小其厚度。 引线框架(10)电连接到半导体芯片(40)。 引线框架包括至少一个引线(17,18),形成在引线上的球接地部分(30)和从球形台面的表面突出以围绕预定区域的凹槽壁(33)。 主体(50)形成为围绕半导体芯片和引线框架。 在由袋壁包围的预定区域的内部布置有焊球(60)。 身体由环氧树脂模塑料组成。 焊球由Sn-Pb系化合物,Sn-Ag系化合物和Sn-Ag-Cu类化合物中的一种构成。

    반도체 패키지용 리드 프레임
    5.
    发明公开
    반도체 패키지용 리드 프레임 无效
    半导体封装的引线框架

    公开(公告)号:KR1020050031600A

    公开(公告)日:2005-04-06

    申请号:KR1020030067800

    申请日:2003-09-30

    Inventor: 송주현 이상국

    Abstract: A lead frame of a semiconductor package is provided to increase a contact area between a molding resin and an integrated circuit chip and reduce thermal stress of a lead frame pad by forming the lead frame pad smaller than the integrated circuit chip and forming a through-hole in a center part of the lead frame pad. A lead frame of a semiconductor package includes a lead frame pad(30). An integrated circuit chip(20) is adhered on the lead frame pad. The lead frame pad has a size smaller than the size of the integrated circuit chip. A through-hole(36) is formed in a center of the lead frame pad. The lead frame pad has a curved side.

    Abstract translation: 提供半导体封装的引线框架,以增加模制树脂和集成电路芯片之间的接触面积,并通过形成小于集成电路芯片的引线框架焊盘来减小引线框架焊盘的热应力,并形成通孔 在引线框架垫的中心部分。 半导体封装的引线框架包括引线框架焊盘(30)。 集成电路芯片(20)粘附在引线框架焊盘上。 引线框焊盘的尺寸小于集成电路芯片的尺寸。 在引线框架焊盘的中心形成有通孔(36)。 引线框架焊盘具有弯曲的一面。

    다이본딩 장치 및 그에 의한 다이본딩 방법
    6.
    发明公开
    다이본딩 장치 및 그에 의한 다이본딩 방법 无效
    DIE结合装置和DIE结合方法

    公开(公告)号:KR1020040042920A

    公开(公告)日:2004-05-22

    申请号:KR1020020070871

    申请日:2002-11-14

    Abstract: PURPOSE: A die bonding apparatus and a die bonding method thereby are provided to be capable of exactly loading a chip on a chip loading part and removing pattern recognition failure. CONSTITUTION: A die bonding apparatus is provided with a semiconductor chip having a micro structure, a support part(100) having a plurality of grooves(108) for stably loading the semiconductor chip, and a chip loading part located at the bottom surface of the grooves for adsorbing the semiconductor chip using vacuum force. Preferably, the upper portion of the groove has a tilt surface(106). Preferably, the semiconductor chip is partially exposed to the outside of the groove. Preferably, the corner generated by the tilt surface is performed with a rounding process.

    Abstract translation: 目的:提供一种芯片接合装置和芯片接合方法,以便能够将芯片精确地加载在芯片加载部分上并去除模式识别故障。 构成:芯片接合装置设置有具有微结构的半导体芯片,具有用于稳定地加载半导体芯片的多个凹槽(108)的支撑部分(100)和位于所述半导体芯片的底表面处的芯片加载部分 用于使用真空力吸附半导体芯片的槽。 优选地,槽的上部具有倾斜表面(106)。 优选地,半导体芯片部分地暴露于凹槽的外部。 优选地,通过舍入处理来执行由倾斜表面产生的角部。

    캐비티가 형성된 내부 리드를 갖는 리드 프레임
    10.
    发明公开
    캐비티가 형성된 내부 리드를 갖는 리드 프레임 无效
    具有内部造型空间的领导框架

    公开(公告)号:KR1020070067283A

    公开(公告)日:2007-06-28

    申请号:KR1020050128395

    申请日:2005-12-23

    Inventor: 송주현

    Abstract: A leadframe having an internal lead with a cavity is provided to insert the ball or stitch of a bonding wire bonded to an internal lead in a wire bonding process into a cavity by forming the cavity in a region to which the bonding wire of the internal lead is bonded. An IC chip(120) is supported by a die pad(112). An internal lead is regularly disposed in the periphery of the die pad, electrically connected to the IC chip by a bonding wire(130). An external lead is extended from the internal lead. At least one cavity(115) is formed in a region of the internal lead to which the bonding wire is bonded. The cavity can be formed on one surface or both surfaces of the internal lead.

    Abstract translation: 提供具有空腔内引线的引线框架,通过在内引线接合线的区域内形成空穴,将引线接合工序中的内引线接合线的球或线迹插入到空腔中 被绑定。 IC芯片(120)由芯片焊盘(112)支撑。 内部引线规则地设置在芯片焊盘的周围,通过接合线(130)与IC芯片电连接。 外部引线从内部引线延伸。 至少一个空腔(115)形成在接合线所接合的内部引线的区域中。 空腔可以形成在内部引线的一个表面或两个表面上。

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